linux-kernel - Re: [PATCH v2 0/4] interconnect: qcom: rpmh: sm8550: mask to send as vote

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <5b68b9ba-157b-067c-3926-9c5ecfecc311@linaro.org>
Date:   Fri, 23 Jun 2023 15:58:09 +0200
From:   Konrad Dybcio <konrad.dybcio@...aro.org>
To:     neil.armstrong@...aro.org, Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Georgi Djakov <djakov@...nel.org>
Cc:     linux-arm-msm@...r.kernel.org, linux-pm@...r.kernel.org,
        linux-kernel@...r.kernel.org, Mike Tipton <mdtipton@...eaurora.org>
Subject: Re: [PATCH v2 0/4] interconnect: qcom: rpmh: sm8550: mask to send as
 vote

On 23.06.2023 14:50, neil.armstrong@...aro.org wrote:
> On the SM8550 SoC, some nodes requires a specific bit mark
> instead of a bandwidth when voting.
> 
> Add an enable_mask variable to be used instead of bandwidth.
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
> ---
After reviewing this patchset and taking a peek at older downstream,
it looks like ACV should be using 0x8 bmask on *all RPMh SoCs*.

It's worth noting however, that 8350's downstream (the first msm
kernel using the icc framework) did not incorporate that change.
Not sure if intentionally or not. Probably not. Might be worth to
poke Qcom to backport it in such case. If 8350 is still supported.
Probably not.

Check out these snippets:

https://git.codelinaro.org/clo/la/kernel/msm-4.19/-/blob/LA.UM.10.2.1.c25/drivers/soc/qcom/msm_bus/msm_bus_arb_rpmh.c#L556-567

https://git.codelinaro.org/clo/la/kernel/msm-4.19/-/blob/LA.UM.10.2.1.c25/drivers/soc/qcom/msm_bus/msm_bus_arb_rpmh.c#L475-495

Notice how acv is never updated beyond effectively setting =0 or =bmask,
perhaps Qualcomm never implemented something else..

Since this series is fine as-is, I'd be happy to see an incremental one.
Reported-by would be cool as well :D

Konrad
> Changes in v2:
> - Took downstream patch for patch 1
> - Added konrad's reviewed tag
> - Added changes for sm8450 and sa8775p
> - Link to v1: https://lore.kernel.org/r/20230619-topic-sm8550-upstream-interconnect-mask-vote-v1-0-66663c0aa592@linaro.org
> 
> ---
> Mike Tipton (1):
>       interconnect: qcom: Add support for mask-based BCMs
> 
> Neil Armstrong (3):
>       interconnect: qcom: sm8450: add enable_mask for bcm nodes
>       interconnect: qcom: sm8550: add enable_mask for bcm nodes
>       interconnect: qcom: sa8775p: add enable_mask for bcm nodes
> 
>  drivers/interconnect/qcom/bcm-voter.c |  5 +++++
>  drivers/interconnect/qcom/icc-rpmh.h  |  2 ++
>  drivers/interconnect/qcom/sa8775p.c   |  1 +
>  drivers/interconnect/qcom/sm8450.c    |  9 +++++++++
>  drivers/interconnect/qcom/sm8550.c    | 17 +++++++++++++++++
>  5 files changed, 34 insertions(+)
> ---
> base-commit: 47045630bc409ce6606d97b790895210dd1d517d
> change-id: 20230619-topic-sm8550-upstream-interconnect-mask-vote-96aa20355158
> 
> Best regards,