linux-kernel - [RFC PATCH 0/6] Add support to handle misaligned accesses in S-mode

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Message-Id: <20230624122049.7886-1-cleger@rivosinc.com>
Date:   Sat, 24 Jun 2023 14:20:43 +0200
From:   Clément Léger <cleger@...osinc.com>
To:     Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Stafford Horne <shorne@...il.com>,
        Brian Cain <bcain@...cinc.com>,
        Kefeng Wang <wangkefeng.wang@...wei.com>,
        "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>,
        Michael Ellerman <mpe@...erman.id.au>,
        Clément Léger <cleger@...osinc.com>,
        Sunil V L <sunilvl@...tanamicro.com>,
        Anup Patel <apatel@...tanamicro.com>,
        Atish Patra <atishp@...osinc.com>,
        Andrew Jones <ajones@...tanamicro.com>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Heiko Stuebner <heiko@...ech.de>, Guo Ren <guoren@...nel.org>,
        Alexandre Ghiti <alexghiti@...osinc.com>,
        Masahiro Yamada <masahiroy@...nel.org>,
        Xianting Tian <xianting.tian@...ux.alibaba.com>,
        Sia Jee Heng <jeeheng.sia@...rfivetech.com>,
        Li Zhengyu <lizhengyu3@...wei.com>,
        Jisheng Zhang <jszhang@...nel.org>,
        "Gautham R. Shenoy" <gautham.shenoy@....com>,
        Mark Rutland <mark.rutland@....com>,
        Peter Zijlstra <peterz@...radead.org>,
        Marc Zyngier <maz@...nel.org>,
        Björn Töpel <bjorn@...osinc.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc:     linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [RFC PATCH 0/6] Add support to handle misaligned accesses in S-mode

Since commit 61cadb9 ("Provide new description of misaligned load/store
behavior compatible with privileged architecture.") in the RISC-V ISA
manual, it is stated that misaligned load/store might not be supported.
However, the RISC-V kernel uABI describes that misaligned accesses are
supported. In order to support that, this series adds support for S-mode
handling of misaligned accesses, SBI call for misaligned trap delegation
as well prctl support for PR_SET_UNALIGN.

Handling misaligned access in kernel allows for a finer grain control
of the misaligned accesses behavior, and thanks to the prctl call, can
allow disabling misaligned access emulation to generate SIGBUS. User
space software can then be optimized by removing such access based on
SIGBUS generation.

This series relies on a SBI extension [1] allowing to request delegation of
the misaligned load/store traps to the S-mode software. This extension
has been submitted for review to the riscv tech-prs group.

This work was tested on spike since Qemu does transparently handles
misaligned access.

[1] https://lists.riscv.org/g/tech-prs/message/472i

Clément Léger (6):
  riscv: remove unused functions in traps_misaligned.c
  riscv: add support for misaligned handling in S-mode
  riscv: allow S-mode to handle misaligned traps
  riscv: add support for SBI misalignment trap delegation
  riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN
  riscv: add floating point insn support to misaligned access emulation

 arch/riscv/include/asm/processor.h   |   9 +
 arch/riscv/include/asm/sbi.h         |  12 ++
 arch/riscv/kernel/Makefile           |   2 +-
 arch/riscv/kernel/fpu.S              | 118 ++++++++++++
 arch/riscv/kernel/process.c          |  20 ++
 arch/riscv/kernel/sbi.c              |  28 +++
 arch/riscv/kernel/traps.c            |   7 -
 arch/riscv/kernel/traps_misaligned.c | 276 ++++++++++++++++++++++-----
 8 files changed, 417 insertions(+), 55 deletions(-)

-- 
2.40.1