linux-kernel - [RFC PATCH 3/6] riscv: allow S-mode to handle misaligned traps

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Message-Id: <20230624122049.7886-4-cleger@rivosinc.com>
Date:   Sat, 24 Jun 2023 14:20:46 +0200
From:   Clément Léger <cleger@...osinc.com>
To:     Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Stafford Horne <shorne@...il.com>,
        Brian Cain <bcain@...cinc.com>,
        Kefeng Wang <wangkefeng.wang@...wei.com>,
        "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>,
        Michael Ellerman <mpe@...erman.id.au>,
        Clément Léger <cleger@...osinc.com>,
        Sunil V L <sunilvl@...tanamicro.com>,
        Anup Patel <apatel@...tanamicro.com>,
        Atish Patra <atishp@...osinc.com>,
        Andrew Jones <ajones@...tanamicro.com>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Heiko Stuebner <heiko@...ech.de>, Guo Ren <guoren@...nel.org>,
        Alexandre Ghiti <alexghiti@...osinc.com>,
        Masahiro Yamada <masahiroy@...nel.org>,
        Xianting Tian <xianting.tian@...ux.alibaba.com>,
        Sia Jee Heng <jeeheng.sia@...rfivetech.com>,
        Li Zhengyu <lizhengyu3@...wei.com>,
        Jisheng Zhang <jszhang@...nel.org>,
        "Gautham R. Shenoy" <gautham.shenoy@....com>,
        Mark Rutland <mark.rutland@....com>,
        Peter Zijlstra <peterz@...radead.org>,
        Marc Zyngier <maz@...nel.org>,
        Björn Töpel <bjorn@...osinc.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc:     linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [RFC PATCH 3/6] riscv: allow S-mode to handle misaligned traps

Now that we will be able to configure the SBI to let us handle the
traps, let this misalignment handling be available for S-mode.

Signed-off-by: Clément Léger <cleger@...osinc.com>
---
 arch/riscv/kernel/traps.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index 8c258b78c925..b544cdd52dd2 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -149,12 +149,6 @@ DO_ERROR_INFO(do_trap_insn_illegal,
 	SIGILL, ILL_ILLOPC, "illegal instruction");
 DO_ERROR_INFO(do_trap_load_fault,
 	SIGSEGV, SEGV_ACCERR, "load access fault");
-#ifndef CONFIG_RISCV_M_MODE
-DO_ERROR_INFO(do_trap_load_misaligned,
-	SIGBUS, BUS_ADRALN, "Oops - load address misaligned");
-DO_ERROR_INFO(do_trap_store_misaligned,
-	SIGBUS, BUS_ADRALN, "Oops - store (or AMO) address misaligned");
-#else
 int handle_misaligned_load(struct pt_regs *regs);
 int handle_misaligned_store(struct pt_regs *regs);
 
@@ -199,7 +193,6 @@ asmlinkage __visible __trap_section void do_trap_store_misaligned(struct pt_regs
 		irqentry_nmi_exit(regs, state);
 	}
 }
-#endif
 DO_ERROR_INFO(do_trap_store_fault,
 	SIGSEGV, SEGV_ACCERR, "store (or AMO) access fault");
 DO_ERROR_INFO(do_trap_ecall_s,
-- 
2.40.1