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Message-Id: <20230624131632.2972546-4-bigunclemax@gmail.com>
Date: Sat, 24 Jun 2023 16:16:24 +0300
From: Maksim Kiselev <bigunclemax@...il.com>
To: linux-spi@...r.kernel.org
Cc: Maksim Kiselev <bigunclemax@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Samuel Holland <samuel@...lland.org>,
Mark Brown <broonie@...nel.org>,
Cristian Ciocaltea <cristian.ciocaltea@...labora.com>,
devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-sunxi@...ts.linux.dev,
linux-kernel@...r.kernel.org
Subject: [PATCH v1 3/3] riscv: dts: allwinner: d1: Add QSPI pins node for pinmux PC port
Add pinmux node that describes pins on PC port which required for
QSPI mode.
Signed-off-by: Maksim Kiselev <bigunclemax@...il.com>
---
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
index 1bb1e5cae602..9f754dd03d85 100644
--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
@@ -131,6 +131,13 @@ uart3_pb_pins: uart3-pb-pins {
pins = "PB6", "PB7";
function = "uart3";
};
+
+ /omit-if-no-ref/
+ qspi0_pc_pins: qspi0-pc-pins {
+ pins = "PC2", "PC3", "PC4", "PC5", "PC6",
+ "PC7";
+ function = "spi0";
+ };
};
ccu: clock-controller@...1000 {
--
2.39.2
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