linux-kernel - Re: [PATCH v1 6/6] arm64: dts: meson: a1: add eMMC controller and its pins

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Message-ID: <41e6d93a-8899-e792-0859-d26360ef5dab@linaro.org>
Date:   Mon, 26 Jun 2023 15:36:23 +0200
From:   neil.armstrong@...aro.org
To:     Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
        Dmitry Rokosov <ddrokosov@...rdevices.ru>
Cc:     jbrunet@...libre.com, mturquette@...libre.com, sboyd@...nel.org,
        robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        khilman@...libre.com, conor+dt@...nel.org, kernel@...rdevices.ru,
        sdfw_system_team@...rdevices.ru, rockosov@...il.com,
        linux-amlogic@...ts.infradead.org, linux-clk@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        Jan Dakinevich <yvdakinevich@...rdevices.ru>
Subject: Re: [PATCH v1 6/6] arm64: dts: meson: a1: add eMMC controller and its
 pins

Hi,

On 25/06/2023 23:11, Martin Blumenstingl wrote:
> On Wed, Jun 7, 2023 at 10:16 PM Dmitry Rokosov <ddrokosov@...rdevices.ru> wrote:
>>
>> From: Jan Dakinevich <yvdakinevich@...rdevices.ru>
>>
>> The definition is inspired by a similar one for AXG SoC family.
>> 'sdio_pins' and 'sdio_clk_gate_pins' pinctrls are supposed to be used as
>> "default" and "clk-gate" in board-specific device trees.
> Let's wait for Neil's response on the other patch for the question
> about pin mux settings
> 
>> 'meson-gx' driver during initialization sets clock to safe low-frequency
>> value (400kHz). However, both source clocks ("clkin0" and "clkin1") are
>> high-frequency by default, and using of eMMC's internal divider is not
>> enough to achieve so low values. To provide low-frequency source,
>> reparent "sd_emmc_sel2" clock using 'assigned-clocks' property.
> Even if the pinctrl part should be postponed then I think it's worth
> adding &sd_emmc

Yeah it's weird to add HW definition and to not enable them,
so please enable them in the board if you add them in the DTSI.

Neil