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Message-Id: <20230627082334.1253020-4-privatesub2@gmail.com>
Date: Tue, 27 Jun 2023 11:23:26 +0300
From: Aleksandr Shubin <privatesub2@...il.com>
To: linux-kernel@...r.kernel.org
Cc: Aleksandr Shubin <privatesub2@...il.com>,
Thierry Reding <thierry.reding@...il.com>,
Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Samuel Holland <samuel@...lland.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Philipp Zabel <p.zabel@...gutronix.de>,
Cristian Ciocaltea <cristian.ciocaltea@...labora.com>,
Andre Przywara <andre.przywara@....com>,
linux-pwm@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-sunxi@...ts.linux.dev,
linux-riscv@...ts.infradead.org
Subject: [PATCH v3 3/3] riscv: dts: allwinner: d1: Add pwm node
D1 and T113s contain a pwm controller with 8 channels.
This controller is supported by the sun20i-pwm driver.
Add a device tree node for it.
Signed-off-by: Aleksandr Shubin <privatesub2@...il.com>
---
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
index 922e8e0e2c09..e24543b6aff7 100644
--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
@@ -127,6 +127,17 @@ uart3_pb_pins: uart3-pb-pins {
};
};
+ pwm: pwm@...0c00 {
+ compatible = "allwinner,sun20i-d1-pwm";
+ reg = <0x02000c00 0x400>;
+ clocks = <&dcxo>,
+ <&ccu CLK_BUS_PWM>;
+ clock-names = "hosc", "bus";
+ resets = <&ccu RST_BUS_PWM>;
+ status = "disabled";
+ #pwm-cells = <0x3>;
+ };
+
ccu: clock-controller@...1000 {
compatible = "allwinner,sun20i-d1-ccu";
reg = <0x2001000 0x1000>;
--
2.25.1
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