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Message-ID: <CAFBinCBYrJGHX-yqCVMm46hdVyaiHrK72Qn8Fj-F623g_Q1SMQ@mail.gmail.com>
Date: Wed, 28 Jun 2023 22:52:30 +0200
From: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To: Huqiang Qin <huqiang.qin@...ogic.com>
Cc: tglx@...utronix.de, maz@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
neil.armstrong@...aro.org, khilman@...libre.com,
jbrunet@...libre.com, hkallweit1@...il.com,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-amlogic@...ts.infradead.org
Subject: Re: [PATCH V2 2/2] irqchip: Add support for Amlogic-C3 SoCs
On Wed, Jun 28, 2023 at 11:16 AM Huqiang Qin <huqiang.qin@...ogic.com> wrote:
>
> The Amlogic-C3 SoCs support 12 GPIO IRQ lines compared with previous
> serial chips and have something different, details are as below.
>
> IRQ Number:
> - 54 1 pins on bank TESTN
> - 53:40 14 pins on bank X
> - 39:33 7 pins on bank D
> - 32:27 6 pins on bank A
> - 26:22 5 pins on bank E
> - 21:15 7 pins on bank C
> - 14:0 15 pins on bank B
>
> Signed-off-by: Huqiang Qin <huqiang.qin@...ogic.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
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