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Message-ID: <20230628131442.3022772-1-sameo@rivosinc.com>
Date: Wed, 28 Jun 2023 15:14:32 +0200
From: Samuel Ortiz <sameo@...osinc.com>
To: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
linux-riscv@...ts.infradead.org
Cc: Samuel Ortiz <sameo@...osinc.com>, linux@...osinc.com,
Conor Dooley <conor.dooley@...rochip.com>,
Andrew Jones <ajones@...tanamicro.com>,
Heiko Stuebner <heiko.stuebner@...ll.eu>,
Anup Patel <apatel@...tanamicro.com>,
linux-kernel@...r.kernel.org,
"Hongren (Zenithal) Zheng" <i@...ithal.me>,
Guo Ren <guoren@...nel.org>, Atish Patra <atishp@...osinc.com>,
Björn Töpel <bjorn@...osinc.com>,
Evan Green <evan@...osinc.com>
Subject: [PATCH v2 0/3] RISC-V: archrandom support
This patchset adds support for the archrandom API to the RISC-V
architecture.
The ratified crypto scalar extensions provide entropy bits via the seed
CSR, as exposed by the Zkr extension.
The first patch of this patchset allows for detecting support of the Zbc
and all scalar crypto extensions.
The second patch exposes the Zbc and scalar crypto extensions through
the hwprobe syscall.
The last patch relies on the first ones to check for the Zkr support,
and implements get_random_seed_longs by looping through a seed CSR
read-write to return one long worth of entropy.
---
v2:
- Fixed the ISA map setting for zkbx
- Alphanumerically sort the ISA map setting
- Added my SOB on Hongren's patch
- Fixed patch #1 commit message
- Remove printk prefix from the archrandom implementation
- Fix needed_seeds computation (and make it const)
- Replace riscv_isa_extension_available() with
riscv_has_extension_likely()
- Make the get_random_seed_longs implementation more readable
---
Hongren (Zenithal) Zheng (1):
RISC-V: add Bitmanip/Scalar Crypto parsing from DT
Samuel Ortiz (2):
RISC-V: hwprobe: Expose Zbc and the scalar crypto extensions
RISC-V: Implement archrandom when Zkr is available
Documentation/riscv/hwprobe.rst | 33 +++++++++++++
arch/riscv/include/asm/archrandom.h | 70 +++++++++++++++++++++++++++
arch/riscv/include/asm/csr.h | 9 ++++
arch/riscv/include/asm/hwcap.h | 11 +++++
arch/riscv/include/uapi/asm/hwprobe.h | 11 +++++
arch/riscv/kernel/cpu.c | 11 +++++
arch/riscv/kernel/cpufeature.c | 30 ++++++++++++
arch/riscv/kernel/sys_riscv.c | 36 ++++++++------
8 files changed, 197 insertions(+), 14 deletions(-)
create mode 100644 arch/riscv/include/asm/archrandom.h
base-commit: 488833ccdcac118da16701f4ee0673b20ba47fe3
--
2.41.0
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