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Message-ID: <9422aa91-4d8c-f51d-26c3-9abed579f62d@quicinc.com>
Date: Wed, 28 Jun 2023 07:52:50 +0530
From: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>
To: Manivannan Sadhasivam <mani@...nel.org>
CC: <manivannan.sadhasivam@...aro.org>, <helgaas@...nel.org>,
<linux-pci@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <quic_vbadigan@...cinc.com>,
<quic_nitegupt@...cinc.com>, <quic_skananth@...cinc.com>,
<quic_ramkri@...cinc.com>, <krzysztof.kozlowski@...aro.org>,
"Lorenzo Pieralisi" <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kw@...ux.com>,
Rob Herring <robh@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>
Subject: Re: [PATCH v5 3/3] PCI: qcom-ep: Add ICC bandwidth voting support
On 6/27/2023 8:31 PM, Manivannan Sadhasivam wrote:
> On Tue, Jun 27, 2023 at 06:31:31AM +0530, Krishna chaitanya chundru wrote:
>> Add support to vote for ICC bandwidth based on the link
>> speed and width.
>>
>> This patch is inspired from pcie-qcom driver to add basic
>> interconnect support.
>>
>> Reference: commit c4860af88d0c ("PCI: qcom: Add basic interconnect
>> support").
>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
>> ---
>> drivers/pci/controller/dwc/pcie-qcom-ep.c | 73 +++++++++++++++++++++++++++++++
>> 1 file changed, 73 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
>> index 1435f51..b613817 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
>> @@ -13,6 +13,7 @@
>> #include <linux/debugfs.h>
>> #include <linux/delay.h>
>> #include <linux/gpio/consumer.h>
>> +#include <linux/interconnect.h>
>> #include <linux/mfd/syscon.h>
>> #include <linux/phy/pcie.h>
>> #include <linux/phy/phy.h>
>> @@ -28,6 +29,7 @@
>> #define PARF_SYS_CTRL 0x00
>> #define PARF_DB_CTRL 0x10
>> #define PARF_PM_CTRL 0x20
>> +#define PARF_PM_STTS 0x24
>> #define PARF_MHI_CLOCK_RESET_CTRL 0x174
>> #define PARF_MHI_BASE_ADDR_LOWER 0x178
>> #define PARF_MHI_BASE_ADDR_UPPER 0x17c
>> @@ -128,11 +130,19 @@
>> /* DBI register fields */
>> #define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0)
>>
>> +#define DBI_LINKCTRLSTATUS 0x80
>> +#define DBI_LINKCTRLSTATUS_SHIFT 16
> not used?
not using these macros so I removed them in next patch.
>> +
>> #define XMLH_LINK_UP 0x400
>> #define CORE_RESET_TIME_US_MIN 1000
>> #define CORE_RESET_TIME_US_MAX 1005
>> #define WAKE_DELAY_US 2000 /* 2 ms */
>>
>> +#define PCIE_GEN1_BW_MBPS 250
>> +#define PCIE_GEN2_BW_MBPS 500
>> +#define PCIE_GEN3_BW_MBPS 985
>> +#define PCIE_GEN4_BW_MBPS 1969
>> +
>> #define to_pcie_ep(x) dev_get_drvdata((x)->dev)
>>
>> enum qcom_pcie_ep_link_status {
>> @@ -178,6 +188,8 @@ struct qcom_pcie_ep {
>> struct phy *phy;
>> struct dentry *debugfs;
>>
>> + struct icc_path *icc_mem;
>> +
>> struct clk_bulk_data *clks;
>> int num_clks;
>>
>> @@ -253,9 +265,51 @@ static void qcom_pcie_dw_stop_link(struct dw_pcie *pci)
>> disable_irq(pcie_ep->perst_irq);
>> }
>>
>> +static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep)
>> +{
>> + struct dw_pcie *pci = &pcie_ep->pci;
>> + u32 offset, status, bw;
>> + int speed, width;
>> + int ret;
>> +
>> + if (!pcie_ep->icc_mem)
>> + return;
>> +
>> + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>> + status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
>> +
>> + speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);
>> + width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
>> +
>> + switch (speed) {
>> + case 1:
>> + bw = MBps_to_icc(PCIE_GEN1_BW_MBPS);
>> + break;
>> + case 2:
>> + bw = MBps_to_icc(PCIE_GEN2_BW_MBPS);
>> + break;
>> + case 3:
>> + bw = MBps_to_icc(PCIE_GEN3_BW_MBPS);
>> + break;
>> + default:
>> + dev_warn(pci->dev, "using default GEN4 bandwidth\n");
>> + fallthrough;
>> + case 4:
>> + bw = MBps_to_icc(PCIE_GEN4_BW_MBPS);
>> + break;
>> + }
>> +
>> + ret = icc_set_bw(pcie_ep->icc_mem, 0, width * bw);
>> + if (ret) {
>> + dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
>> + ret);
> No need of braces for single line.
done.
>> + }
>> +}
>> +
>> static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
>> {
>> int ret;
>> + struct dw_pcie *pci = &pcie_ep->pci;
>>
>> ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks);
>> if (ret)
>> @@ -277,6 +331,20 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
>> if (ret)
>> goto err_phy_exit;
>>
>> + /*
>> + * Some Qualcomm platforms require interconnect bandwidth constraints
>> + * to be set before enabling interconnect clocks.
>> + *
>> + * Set an initial peak bandwidth corresponding to single-lane Gen 1
>> + * for the pcie-mem path.
>> + */
>> + ret = icc_set_bw(pcie_ep->icc_mem, 0, MBps_to_icc(PCIE_GEN1_BW_MBPS));
>> + if (ret) {
>> + dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
>> + ret);
>> + goto err_phy_exit;
> Again, you should power off the PHY in the case of error. err_phy_exit is not
> doing that for you.
>
> - Mani
added the code remove the phy power.
-KC
>> + }
>> +
>> return 0;
>>
>> err_phy_exit:
>> @@ -550,6 +618,10 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev,
>> if (IS_ERR(pcie_ep->phy))
>> ret = PTR_ERR(pcie_ep->phy);
>>
>> + pcie_ep->icc_mem = devm_of_icc_get(dev, "pcie-mem");
>> + if (IS_ERR(pcie_ep->icc_mem))
>> + ret = PTR_ERR(pcie_ep->icc_mem);
>> +
>> return ret;
>> }
>>
>> @@ -573,6 +645,7 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data)
>> } else if (FIELD_GET(PARF_INT_ALL_BME, status)) {
>> dev_dbg(dev, "Received BME event. Link is enabled!\n");
>> pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED;
>> + qcom_pcie_ep_icc_update(pcie_ep);
>> pci_epc_bme_notify(pci->ep.epc);
>> } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) {
>> dev_dbg(dev, "Received PM Turn-off event! Entering L23\n");
>> --
>> 2.7.4
>>
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