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Message-ID: <dc30a8c6-c313-9d85-c41e-07171dfdf056@intel.com>
Date: Wed, 28 Jun 2023 17:32:13 -0700
From: Dave Hansen <dave.hansen@...el.com>
To: Nikolay Borisov <nik.borisov@...e.com>,
Kai Huang <kai.huang@...el.com>, linux-kernel@...r.kernel.org,
kvm@...r.kernel.org
Cc: linux-mm@...ck.org, x86@...nel.org,
kirill.shutemov@...ux.intel.com, tony.luck@...el.com,
peterz@...radead.org, tglx@...utronix.de, bp@...en8.de,
mingo@...hat.com, hpa@...or.com, seanjc@...gle.com,
pbonzini@...hat.com, david@...hat.com, dan.j.williams@...el.com,
rafael.j.wysocki@...el.com, ashok.raj@...el.com,
reinette.chatre@...el.com, len.brown@...el.com, ak@...ux.intel.com,
isaku.yamahata@...el.com, ying.huang@...el.com, chao.gao@...el.com,
sathyanarayanan.kuppuswamy@...ux.intel.com, bagasdotme@...il.com,
sagis@...gle.com, imammedo@...hat.com
Subject: Re: [PATCH v12 19/22] x86/kexec(): Reset TDX private memory on
platforms with TDX erratum
On 6/28/23 02:20, Nikolay Borisov wrote:
>>
>> + /*
>> + * Starting from this point the system may have TDX private
>> + * memory. Make it globally visible so tdx_reset_memory() only
>> + * reads TDMRs/PAMTs when they are stable.
>> + *
>> + * Note using atomic_inc_return() to provide the explicit memory
>> + * ordering isn't mandatory here as the WBINVD above already
>> + * does that. Compiler barrier isn't needed here either.
>> + */
>
> If it's not needed, then why use it? Simply do atomic_inc() and instead
> rephrase the comment to state what are the ordering guarantees and how
> they are achieved (i.e by using wbinvd above).
Even better, explain why the barrier needs to be there and *IGNORE* the
WBVIND.
If the WBINVD gets moved -- or if the gods ever bless us with a halfway
reasonable way to flush the caches that's not full serializing -- this
code is screwed.
There is _zero_ reason to try and "optimize" this junk by trying to get
rid of a memory barrier at the risk of screwing it over later.
I use "optimize" in quotes because that's a highly charitable way of
describing this activity.
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