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Message-ID: <1688015537-31682-5-git-send-email-spujar@nvidia.com>
Date: Thu, 29 Jun 2023 10:42:16 +0530
From: Sameer Pujar <spujar@...dia.com>
To: <broonie@...nel.org>, <robh+dt@...nel.org>, <krzk+dt@...nel.org>,
<thierry.reding@...il.com>, <lgirdwood@...il.com>,
<perex@...ex.cz>, <tiwai@...e.com>
CC: <jonathanh@...dia.com>, <mkumard@...dia.com>, <sheetal@...dia.com>,
<spujar@...dia.com>, <alsa-devel@...a-project.org>,
<devicetree@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <stable@...r.kernel.org>
Subject: [PATCH v2 4/5] arm64: tegra: Update AHUB clock parent and rate on Tegra234
From: Sheetal <sheetal@...dia.com>
I2S data sanity tests fail beyond a bit clock frequency of 6.144MHz.
This happens because the AHUB clock rate is too low and it shows
9.83MHz on boot.
The maximum rate of PLLA_OUT0 is 49.152MHz and is used to serve I/O
clocks. It is recommended that AHUB clock operates higher than this.
Thus fix this by using PLLP_OUT0 as parent clock for AHUB instead of
PLLA_OUT0 and fix the rate to 81.6MHz.
Fixes: dc94a94daa39 ("arm64: tegra: Add audio devices on Tegra234")
Cc: stable@...r.kernel.org
Signed-off-by: Sheetal <sheetal@...dia.com>
Signed-off-by: Sameer Pujar <spujar@...dia.com>
Reviewed-by: Mohan Kumar D <mkumard@...dia.com>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index f4974e8..0f12a8de 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -180,7 +180,8 @@
clocks = <&bpmp TEGRA234_CLK_AHUB>;
clock-names = "ahub";
assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
- assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+ assigned-clock-rates = <81600000>;
status = "disabled";
#address-cells = <2>;
--
2.7.4
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