[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <924ebd8b-2e1f-4060-8c66-4f4746e88696@lunn.ch>
Date: Fri, 30 Jun 2023 15:21:49 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Jie Luo <quic_luoj@...cinc.com>
Cc: hkallweit1@...il.com, davem@...emloft.net, edumazet@...gle.com,
kuba@...nel.org, pabeni@...hat.com, linux@...linux.org.uk,
netdev@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link
down
> SERDES device is the block converts data between serial data and parallel
> interfaces in each direction, which is the SGMII interface in qca8081 PHY,
> it's address is always the PHY address added by 1 in qca8081 PHY.
What other registers does this block have? What behaviour can be
configured? Does it have any support for Clause 73? Is there an open
datasheet for it?
Andrew
Powered by blists - more mailing lists