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Date:   Fri, 30 Jun 2023 17:21:24 +0200
From:   Roman Kagan <rkagan@...zon.de>
To:     Sean Christopherson <seanjc@...gle.com>
CC:     Jim Mattson <jmattson@...gle.com>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Eric Hankland <ehankland@...gle.com>, <kvm@...r.kernel.org>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        Like Xu <likexu@...cent.com>, <x86@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        <linux-kernel@...r.kernel.org>, "H. Peter Anvin" <hpa@...or.com>,
        "Borislav Petkov" <bp@...en8.de>, Ingo Molnar <mingo@...hat.com>,
        Mingwei Zhang <mizhang@...gle.com>
Subject: Re: [PATCH] KVM: x86: vPMU: truncate counter value to allowed width

On Fri, Jun 30, 2023 at 07:28:29AM -0700, Sean Christopherson wrote:
> On Fri, Jun 30, 2023, Roman Kagan wrote:
> > On Thu, Jun 29, 2023 at 05:11:06PM -0700, Sean Christopherson wrote:
> > > @@ -74,6 +74,14 @@ static inline u64 pmc_read_counter(struct kvm_pmc *pmc)
> > >         return counter & pmc_bitmask(pmc);
> > >  }
> > >
> > > +static inline void pmc_write_counter(struct kvm_pmc *pmc, u64 val)
> > > +{
> > > +       if (pmc->perf_event && !pmc->is_paused)
> > > +               perf_event_set_count(pmc->perf_event, val);
> > > +
> > > +       pmc->counter = val;
> >
> > Doesn't this still have the original problem of storing wider value than
> > allowed?
> 
> Yes, this was just to fix the counter offset weirdness.  My plan is to apply your
> patch on top.  Sorry for not making that clear.

Ah, got it, thanks!

Also I'm now chasing a problem that we occasionally see

[3939579.462832] Uhhuh. NMI received for unknown reason 30 on CPU 43.
[3939579.462836] Do you have a strange power saving mode enabled?
[3939579.462836] Dazed and confused, but trying to continue

in the guests when perf is used.  These messages disappear when
9cd803d496e7 ("KVM: x86: Update vPMCs when retiring instructions") is
reverted.  I haven't yet figured out where exactly the culprit is.

Thanks,
Roman.



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