linux-kernel - [PATCH 1/4] pinctrl: amd: Only use special debounce behavior for GPIO 0

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Message-ID: <20230630194716.6497-2-mario.limonciello@amd.com>
Date:   Fri, 30 Jun 2023 14:47:13 -0500
From:   Mario Limonciello <mario.limonciello@....com>
To:     <Basavaraj.Natikar@....com>, <Shyam-sundar.S-k@....com>,
        <linus.walleij@...aro.org>
CC:     <npliashechnikov@...il.com>, <nmschulte@...il.com>,
        <friedrich.vock@....de>, <dridri85@...il.com>,
        <linux-gpio@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        Mario Limonciello <mario.limonciello@....com>,
        <stable@...r.kernel.org>
Subject: [PATCH 1/4] pinctrl: amd: Only use special debounce behavior for GPIO 0

It's uncommon to use debounce on any other pin, but technically
we should only set debounce to 0 when working off GPIO0.

Cc: stable@...r.kernel.org
Fixes: 968ab9261627f ("pinctrl: amd: Detect internal GPIO0 debounce handling")
Signed-off-by: Mario Limonciello <mario.limonciello@....com>
---
 drivers/pinctrl/pinctrl-amd.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 7a4dd0c861abc..02d9f9f245707 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -127,9 +127,11 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
 
 	/* Use special handling for Pin0 debounce */
-	pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
-	if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
-		debounce = 0;
+	if (offset == 0) {
+		pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
+		if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
+			debounce = 0;
+	}
 
 	pin_reg = readl(gpio_dev->base + offset * 4);
 
-- 
2.34.1