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Message-ID: <649f6e34d4386_14494294e2@dwillia2-mobl3.amr.corp.intel.com.notmuch>
Date: Fri, 30 Jun 2023 17:07:16 -0700
From: Dan Williams <dan.j.williams@...el.com>
To: <torvalds@...ux-foundation.org>
CC: <linux-cxl@...r.kernel.org>, <linux-pci@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
Subject: [GIT PULL] Compute Express Link (CXL) for 6.5
Hi Linus, please pull from:
git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl tags/cxl-for-6.5
...to receive the CXL update for this cycle. The highlights in terms of
new functionality are support for the standard CXL Performance Monitor
definition that appeared in CXL 3.0, support for device sanitization
(wiping all data from a device), secure-erase (re-keying encryption of
user data), and support for firmware update. The firmware update support
is notable as it reuses the simple sysfs_upload interface to just cat(1)
a blob to a sysfs file and pipe that to the device.
Additionally there are a substantial number of cleanups and
reorganizations to get ready for RCH error handling (RCH == Restricted
CXL Host == current shipping hardware generation / pre CXL-2.0
topologies) and type-2 (accelerator / vendor specific) devices.
For vendor specific devices they implement a subset of what the generic
type-3 (generic memory expander) driver expects. As a result the rework
decouples optional infrastructure from the core driver context.
For RCH topologies, where the specification working group did not want
to confuse pre-CXL-aware operating systems, many of the standard
registers are hidden which makes support standard bus features like AER
(PCIe Advanced Error Reporting) difficult. The rework arranges for the
driver to help the PCI-AER core. Bjorn is on board with this direction
but a late regression disocvery means the completion of this
functionality needs to cook a bit longer, so it is code reorganizations
only for now.
It has all appeared in linux-next. Stephen did report that one of the
Fixes: tags has an 11-character rather than 12-character abbreviated
commit id. That submitter has updated their gitconfig going forward.
There is also one late kernel-doc fixup that I missed when merging the
driver-context decoupling with the new background command facilities.
---
The following changes since commit 858fd168a95c5b9669aac8db6c14a9aeab446375:
Linux 6.4-rc6 (2023-06-11 14:35:30 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl tags/cxl-for-6.5
for you to fetch changes up to fe77cc2e5a6a7c85f5c6ef8a39d7694ffc7f41c9:
cxl: Fix one kernel-doc comment (2023-06-29 16:03:58 -0700)
----------------------------------------------------------------
cxl for v6.5
- Add infrastructure for supporting background commands along with
support for device sanitization and firmware update
- Introduce a CXL performance monitoring unit driver based on the common
definition in the specification.
- Land some preparatory cleanup and refactoring for the anticipated
arrival of CXL type-2 (accelerator devices) and CXL RCH (CXL-v1.1
topology) error handling.
- Rework CPU cache management with respect to region configuration
(device hotplug or other dynamic changes to memory interleaving)
- Fix region reconfiguration vs CXL decoder ordering rules.
----------------------------------------------------------------
Dan Williams (23):
cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability
cxl: Rename 'uport' to 'uport_dev'
cxl/region: Move cache invalidation before region teardown, and before setup
cxl/region: Flag partially torn down regions as unusable
cxl/region: Fix state transitions after reset failure
cxl/regs: Clarify when a 'struct cxl_register_map' is input vs output
tools/testing/cxl: Remove unused @cxlds argument
cxl: Fix kernel-doc warnings
cxl: Remove leftover attribute documentation in 'struct cxl_dev_state'
cxl/mbox: Move mailbox related driver state to its own data structure
cxl/memdev: Make mailbox functionality optional
cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}
cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM
cxl/region: Manage decoder target_type at decoder-attach time
cxl/pci: Unconditionally unmask 256B Flit errors
cxl/memdev: Formalize endpoint port linkage
Revert "cxl/port: Enable the HDM decoder capability for switch ports"
Merge branch 'for-6.5/cxl-background' into for-6.5/cxl
Merge branch 'for-6.5/cxl-fwupd' into for-6.5/cxl
Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxl
Merge branch 'for-6.5/cxl-region-fixes' into for-6.5/cxl
Merge branch 'for-6.5/cxl-perf' into for-6.5/cxl
Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl
Davidlohr Bueso (12):
rcuwait: Support timeouts
cxl/pci: Allocate irq vectors earlier during probe
cxl/pci: Introduce cxl_request_irq()
cxl/mbox: Add background cmd handling machinery
cxl/mbox: Allow for IRQ_NONE case in the isr
cxl/mem: Introduce security state sysfs file
cxl/mbox: Add sanitization handling machinery
cxl/mem: Wire up Sanitization support
cxl/test: Add Sanitize opcode support
cxl/mem: Support Secure Erase
cxl/test: Add Secure Erase opcode support
cxl/pci: Use correct flag for sanitize polling
Jonathan Cameron (5):
perf: Allow a PMU to have a parent
cxl: Add functions to get an instance of / count regblocks of a given type
cxl/pci: Find and register CXL PMU devices
perf: CXL Performance Monitoring Unit driver
docs: perf: Minimal introduction the the CXL PMU device and driver
Robert Richter (11):
cxl/acpi: Probe RCRB later during RCH downstream port creation
cxl: Rename member @dport of struct cxl_dport to @dport_dev
cxl/core/regs: Add @dev to cxl_register_map
cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs()
cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port
cxl/port: Remove Component Register base address from struct cxl_dport
cxl/regs: Remove early capability checks in Component Register setup
cxl/mem: Prepare for early RCH dport component register setup
cxl/pci: Early setup RCH dport component registers from RCRB
cxl/port: Store the port's Component Register mappings in struct cxl_port
cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport
Terry Bowman (1):
cxl/pci: Refactor component register discovery for reuse
Vishal Verma (4):
cxl: add a firmware update mechanism using the sysfs firmware loader
tools/testing/cxl: Fix command effects for inject/clear poison
tools/testing/cxl: Use named effects for the Command Effect Log
tools/testing/cxl: add firmware update emulation to CXL memdevs
Yang Li (1):
cxl: Fix one kernel-doc comment
Documentation/ABI/testing/sysfs-bus-cxl | 48 ++
Documentation/admin-guide/perf/cxl.rst | 68 +++
Documentation/admin-guide/perf/index.rst | 1 +
MAINTAINERS | 7 +
drivers/cxl/Kconfig | 14 +
drivers/cxl/acpi.c | 208 ++++---
drivers/cxl/core/Makefile | 1 +
drivers/cxl/core/core.h | 11 +
drivers/cxl/core/hdm.c | 48 +-
drivers/cxl/core/mbox.c | 339 ++++++-----
drivers/cxl/core/memdev.c | 503 +++++++++++++++-
drivers/cxl/core/pci.c | 31 +-
drivers/cxl/core/pmem.c | 2 +-
drivers/cxl/core/pmu.c | 68 +++
drivers/cxl/core/port.c | 163 +++--
drivers/cxl/core/region.c | 168 ++++--
drivers/cxl/core/regs.c | 182 +++++-
drivers/cxl/cxl.h | 104 ++--
drivers/cxl/cxlmem.h | 229 +++++--
drivers/cxl/cxlpci.h | 1 +
drivers/cxl/mem.c | 26 +-
drivers/cxl/pci.c | 486 ++++++++++-----
drivers/cxl/pmem.c | 35 +-
drivers/cxl/pmu.h | 28 +
drivers/cxl/port.c | 21 +-
drivers/cxl/security.c | 27 +-
drivers/perf/Kconfig | 13 +
drivers/perf/Makefile | 1 +
drivers/perf/cxl_pmu.c | 990 +++++++++++++++++++++++++++++++
include/linux/perf_event.h | 1 +
include/linux/rcuwait.h | 23 +-
kernel/events/core.c | 1 +
tools/testing/cxl/Kbuild | 5 +-
tools/testing/cxl/test/cxl.c | 36 +-
tools/testing/cxl/test/mem.c | 367 +++++++++---
tools/testing/cxl/test/mock.c | 59 +-
tools/testing/cxl/test/mock.h | 3 -
37 files changed, 3475 insertions(+), 843 deletions(-)
create mode 100644 Documentation/admin-guide/perf/cxl.rst
create mode 100644 drivers/cxl/core/pmu.c
create mode 100644 drivers/cxl/pmu.h
create mode 100644 drivers/perf/cxl_pmu.c
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