| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <83459098-5fe5-37e9-45fd-f9d2daca7221@linaro.org>
Date: Mon, 3 Jul 2023 11:31:57 +0200
From: Neil Armstrong <neil.armstrong@...aro.org>
To: Xianwei Zhao <xianwei.zhao@...ogic.com>,
Lucas Tanure <tanure@...ux.com>
Cc: Nick <nick@...das.com>, Artem <art@...das.com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-amlogic@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Jerome Brunet <jbrunet@...libre.com>,
Kevin Hilman <khilman@...libre.com>
Subject: Re: [PATCH v7 4/4] arm64: dts: amlogic-t7-a311d2-khadas-vim4: add
initial device-tree
Hi,
On 03/07/2023 04:39, Xianwei Zhao wrote:
>
>
> On 2023/6/29 15:34, Lucas Tanure wrote:
>> [ EXTERNAL EMAIL ]
>>
>> The Khadas VIM4 uses the Amlogic A311D2 SoC, based on the Amlogic T7 SoC
>> family, on a board with the same form factor as the VIM3 models.
>>
>> - 8GB LPDDR4X 2016MHz
>> - 32GB eMMC 5.1 storage
>> - 32MB SPI flash
>> - 10/100/1000 Base-T Ethernet
>> - AP6275S Wireless (802.11 a/b/g/n/ac/ax, BT5.1)
>> - HDMI 2.1 video
>> - HDMI Input
>> - 1x USB 2.0 + 1x USB 3.0 ports
>> - 1x USB-C (power) with USB 2.0 OTG
>> - 3x LED's (1x red, 1x blue, 1x white)
>> - 3x buttons (power, function, reset)
>> - M2 socket with PCIe, USB, ADC & I2C
>> - 40pin GPIO Header
>> - 1x micro SD card slot
>>
>> Signed-off-by: Lucas Tanure <tanure@...ux.com>
>> ---
>> arch/arm64/boot/dts/amlogic/Makefile | 1 +
>> .../amlogic/amlogic-t7-a311d2-khadas-vim4.dts | 54 ++++++
>> arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 155 ++++++++++++++++++
>> 3 files changed, 210 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
>> create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
>> index cd1c5b04890a..166fec1e4229 100644
>> --- a/arch/arm64/boot/dts/amlogic/Makefile
>> +++ b/arch/arm64/boot/dts/amlogic/Makefile
>> @@ -1,4 +1,5 @@
>> # SPDX-License-Identifier: GPL-2.0
>> +dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb
>> dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb
>> dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb
>> dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j110-rev-2.dtb
>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
>> new file mode 100644
>> index 000000000000..fffdab96b12e
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
>> @@ -0,0 +1,54 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2022 Wesion, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "amlogic-t7.dtsi"
>> +
>> +/ {
>> + model = "Khadas vim4";
>> + compatible = "khadas,vim4", "amlogic,a311d2", "amlogic,t7";
>> +
>> + aliases {
>> + serial0 = &uart_a;
>> + };
>> +
>> + memory@0 {
>> + device_type = "memory";
>> + reg = <0x0 0x0 0x2 0x0>; /* 8 GB */
>> + };
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
>> + secmon_reserved: secmon@...0000 {
>> + reg = <0x0 0x05000000 0x0 0x300000>;
>> + no-map;
>> + };
>> +
>> + /* 32 MiB reserved for ARM Trusted Firmware (BL32) */
>> + secmon_reserved_bl32: secmon@...0000 {
>> + reg = <0x0 0x05300000 0x0 0x2000000>;
>> + no-map;
>> + };
>> + };
>> +
>> + xtal: xtal-clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <24000000>;
>> + clock-output-names = "xtal";
>> + #clock-cells = <0>;
>> + };
> Place xal in DTSI files is beterr, the same as other Amlogic SoCs family. If frequency is different, reset value in here.
It's expected to have xtal in the board dts, since it's part of the board not the SoC.
Neil
>
>> +
>> +};
>> +
>> +&uart_a {
>> + status = "okay";
>> + clocks = <&xtal>, <&xtal>, <&xtal>;
>> + clock-names = "xtal", "pclk", "baud";
>> +};
>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> new file mode 100644
>> index 000000000000..1423d4a79156
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> @@ -0,0 +1,155 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/ {
>> + interrupt-parent = <&gic>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + cpus {
>> + #address-cells = <0x2>;
>> + #size-cells = <0x0>;
>> +
>> + cpu-map {
>> + cluster0 {
>> + core0 {
>> + cpu = <&cpu100>;
>> + };
>> + core1 {
>> + cpu = <&cpu101>;
>> + };
>> + core2 {
>> + cpu = <&cpu102>;
>> + };
>> + core3 {
>> + cpu = <&cpu103>;
>> + };
>> + };
>> +
>> + cluster1 {
>> + core0 {
>> + cpu = <&cpu0>;
>> + };
>> + core1 {
>> + cpu = <&cpu1>;
>> + };
>> + core2 {
>> + cpu = <&cpu2>;
>> + };
>> + core3 {
>> + cpu = <&cpu3>;
>> + };
>> + };
>> + };
>> +
>> + cpu100: cpu@100 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53";
>> + reg = <0x0 0x100>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu101: cpu@...{
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53";
>> + reg = <0x0 0x101>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu102: cpu@102 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53";
>> + reg = <0x0 0x102>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu103: cpu@103 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53";
>> + reg = <0x0 0x103>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu0: cpu@0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a73";
>> + reg = <0x0 0x0>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu1: cpu@1 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a73";
>> + reg = <0x0 0x1>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu2: cpu@2 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a73";
>> + reg = <0x0 0x2>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu3: cpu@3 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a73";
>> + reg = <0x0 0x3>;
>> + enable-method = "psci";
>> + };
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
>> + };
>> +
>> + psci {
>> + compatible = "arm,psci-1.0";
>> + method = "smc";
>> + };
>> +
>> + sm: secure-monitor {
>> + compatible = "amlogic,meson-gxbb-sm";
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + gic: interrupt-controller@...01000 {
>> + compatible = "arm,gic-400";
>> + #interrupt-cells = <3>;
>> + #address-cells = <0>;
>> + interrupt-controller;
>> + reg = <0x0 0xfff01000 0 0x1000>,
>> + <0x0 0xfff02000 0 0x0100>;
>> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
>> + };
>> +
>> + apb4: bus@...00000 {
>> + compatible = "simple-bus";
>> + reg = <0x0 0xfe000000 0x0 0x480000>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
>> +
>> + uart_a: serial@...00 {
>> + compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart";
>> + reg = <0x0 0x78000 0x0 0x18>;
>> + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> + status = "disabled";
>> + };
>> + };
>> +
>> + };
>> +};
>> --
>> 2.41.0
>>
Powered by blists - more mailing lists