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Message-ID: <014d01d9ad5f$2c426f30$84c74d90$@samsung.com>
Date:   Mon, 3 Jul 2023 09:03:38 +0530
From:   "Alim Akhtar" <alim.akhtar@...sung.com>
To:     "'Krzysztof Kozlowski'" <krzysztof.kozlowski@...aro.org>,
        "'Rob Herring'" <robh+dt@...nel.org>,
        "'Krzysztof Kozlowski'" <krzysztof.kozlowski+dt@...aro.org>,
        "'Conor Dooley'" <conor+dt@...nel.org>, <linux-fsd@...la.com>,
        <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-samsung-soc@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 2/4] arm64: dts: fsd: minor whitespace cleanup around
 '='

Hi Krzysztof,

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Sent: Monday, July 3, 2023 12:20 AM
> To: Rob Herring <robh+dt@...nel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@...aro.org>; Conor Dooley
> <conor+dt@...nel.org>; Alim Akhtar <alim.akhtar@...sung.com>; linux-
> fsd@...la.com; devicetree@...r.kernel.org; linux-arm-
> kernel@...ts.infradead.org; linux-samsung-soc@...r.kernel.org; linux-
> kernel@...r.kernel.org
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Subject: [PATCH 2/4] arm64: dts: fsd: minor whitespace cleanup around '='
> 
> The DTS code coding style expects exactly one space before and after '='
> sign.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> ---

Thanks!
Reviewed-by: Alim Akhtar <alim.akhtar@...sung.com>

>  arch/arm64/boot/dts/tesla/fsd.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi
> b/arch/arm64/boot/dts/tesla/fsd.dtsi
> index 1c53c68efd53..bb50a9f7db4a 100644
> --- a/arch/arm64/boot/dts/tesla/fsd.dtsi
> +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
> @@ -353,8 +353,8 @@ gic: interrupt-controller@...00000 {
>  			compatible = "arm,gic-v3";
>  			#interrupt-cells = <3>;
>  			interrupt-controller;
> -			reg =	<0x0 0x10400000 0x0 0x10000>, /* GICD */
> -				<0x0 0x10600000 0x0 0x200000>; /*
> GICR_RD+GICR_SGI */
> +			reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */
> +			      <0x0 0x10600000 0x0 0x200000>; /*
> GICR_RD+GICR_SGI */
>  			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>  		};
> 
> --
> 2.34.1


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