linux-kernel - Re: [PATCH v8 01/14] cxl/port: Pre-initialize component register mappings

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Message-ID: <20230703192936.00003dbd@Huawei.com>
Date:   Mon, 3 Jul 2023 19:29:36 +0800
From:   Jonathan Cameron <Jonathan.Cameron@...wei.com>
To:     Terry Bowman <terry.bowman@....com>
CC:     <alison.schofield@...el.com>, <vishal.l.verma@...el.com>,
        <ira.weiny@...el.com>, <bwidawsk@...nel.org>,
        <dan.j.williams@...el.com>, <dave.jiang@...el.com>,
        <linux-cxl@...r.kernel.org>, <rrichter@....com>,
        <linux-kernel@...r.kernel.org>, <bhelgaas@...gle.com>
Subject: Re: [PATCH v8 01/14] cxl/port: Pre-initialize component register
 mappings

On Fri, 30 Jun 2023 18:16:22 -0500
Terry Bowman <terry.bowman@....com> wrote:

> From: Robert Richter <rrichter@....com>
> 
> The component registers of a component may not exist or are not
> needed. The setup may fail for that reason. In some cases the
> initialization should continue anyway. Thus, always initialize struct
> cxl_register_map with valid values. In case of errors, zero it, set a
> value for @dev and make @resource a the valid value using
> CXL_RESOURCE_NONE.
> 
> Signed-off-by: Robert Richter <rrichter@....com>
> Signed-off-by: Terry Bowman <terry.bowman@....com>
Seems reasonable to me.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>

> ---
>  drivers/cxl/core/port.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 724be8448eb4..2d22e7a5629b 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -693,16 +693,17 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
>  static int cxl_setup_comp_regs(struct device *dev, struct cxl_register_map *map,
>  			       resource_size_t component_reg_phys)
>  {
> -	if (component_reg_phys == CXL_RESOURCE_NONE)
> -		return 0;
> -
>  	*map = (struct cxl_register_map) {
>  		.dev = dev,
> -		.reg_type = CXL_REGLOC_RBI_COMPONENT,
>  		.resource = component_reg_phys,
> -		.max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
>  	};
>  
> +	if (component_reg_phys == CXL_RESOURCE_NONE)
> +		return 0;
> +
> +	map->reg_type = CXL_REGLOC_RBI_COMPONENT;
> +	map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE;
> +
>  	return cxl_setup_regs(map);
>  }
>