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Message-ID: <20230703125419.GJ4253@hirez.programming.kicks-ass.net>
Date: Mon, 3 Jul 2023 14:54:19 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: Borislav Petkov <bp@...en8.de>
Cc: X86 ML <x86@...nel.org>,
Kishon VijayAbraham <Kishon.VijayAbraham@....com>,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] x86/barrier: Do not serialize MSR accesses on AMD
On Thu, Jun 22, 2023 at 11:52:12AM +0200, Borislav Petkov wrote:
> From: "Borislav Petkov (AMD)" <bp@...en8.de>
>
> AMD does not have the requirement for a synchronization barrier when
> acccessing a certain group of MSRs. Do not incur that unnecessary
> penalty there.
So you're saying that AMD tsc_deadline and x2apic MSRs *do* imply
ordering constraints unlike the Intel ones?
Can we pls haz a document link for that, also a comment?
> Signed-off-by: Borislav Petkov (AMD) <bp@...en8.de>
> ---
> arch/x86/include/asm/barrier.h | 18 ------------------
> arch/x86/include/asm/processor.h | 19 +++++++++++++++++++
> 2 files changed, 19 insertions(+), 18 deletions(-)
Moving this code while changing it meant I had to look at it _3_ times
before I spotted you changed it :/
> diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
> index b216ac80ebcc..983406342484 100644
> --- a/arch/x86/include/asm/processor.h
> +++ b/arch/x86/include/asm/processor.h
> @@ -735,4 +735,23 @@ bool arch_is_platform_page(u64 paddr);
> #define arch_is_platform_page arch_is_platform_page
> #endif
>
> +/*
> + * Make previous memory operations globally visible before
> + * a WRMSR.
> + *
> + * MFENCE makes writes visible, but only affects load/store
> + * instructions. WRMSR is unfortunately not a load/store
> + * instruction and is unaffected by MFENCE. The LFENCE ensures
> + * that the WRMSR is not reordered.
> + *
> + * Most WRMSRs are full serializing instructions themselves and
> + * do not require this barrier. This is only required for the
> + * IA32_TSC_DEADLINE and X2APIC MSRs.
> + */
> +static inline void weak_wrmsr_fence(void)
> +{
> + if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
> + asm volatile("mfence; lfence" : : : "memory");
Both instructions are 3 bytes, a 6 byte nop would be better, no?
asm volatile (ALTERNATIVE("mfence; lfence;", "", X86_FEATURE_AMD));
or something ?
> +}
> +
> #endif /* _ASM_X86_PROCESSOR_H */
> --
> 2.35.1
>
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