lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <1891c041807.fea67a55448140.3454059194195387266@linux.beauty>
Date:   Mon, 03 Jul 2023 21:49:37 +0800
From:   Li Chen <me@...ux.beauty>
To:     "Achal Verma" <a-verma1@...com>
Cc:     "Vignesh Raghavendra" <vigneshr@...com>,
        "Tom Joseph" <tjoseph@...ence.com>,
        "Lorenzo Pieralisi" <lpieralisi@...nel.org>,
        "Krzysztof Wilczy_ski" <kw@...ux.com>,
        "Rob Herring" <robh@...nel.org>,
        "Bjorn Helgaas" <bhelgaas@...gle.com>,
        "linux-omap" <linux-omap@...r.kernel.org>,
        "linux-pci" <linux-pci@...r.kernel.org>,
        "linux-arm-kernel" <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] PCI: j721e: Fix delay before PERST# deassert

Hi Achal,
 ---- On Mon, 03 Jul 2023 19:29:14 +0800  Achal Verma  wrote --- 
 > As per the PCIe Card Electromechanical specification REV. 3.0, PERST#
 > signal should be de-asserted after minimum 100ms from the time power-rails
 > become stable. Current delay of 100us is observed to be not enough on some
 > custom platform implemented using TI's K3 SOCs.
 > 
 > So, to ensure 100ms delay to give sufficient time for power-rails and
 > refclk to become stable, change delay from 100us to 100ms.

What problems could arise if the delay is too small? Would some endpoints not be able to detect it?

Regards,
Li

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ