| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Tue, 4 Jul 2023 20:05:30 +0800
From: LeoLiu-oc <LeoLiu-oc@...oxin.com>
To: <lenb@...nel.org>, <james.morse@....com>, <tony.luck@...el.com>,
<bp@...en8.de>, <bhelgaas@...gle.com>, <robert.moore@...el.com>,
<leoliu-oc@...oxin.com>, <linux-acpi@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-pci@...r.kernel.org>,
<acpica-devel@...ts.linuxfoundation.org>
Subject: [PATCH v3 3/5] PCI: Add PCIe to PCI/PCI-X Bridge AER fields
From: leoliu-oc <leoliu-oc@...oxin.com>
Define Secondary Uncorrectable Error Mask Register, Secondary
Uncorrectable Error Severity Register and Secondary Error Capabilities and
Control Register bits in AER capability for PCIe to PCI/PCI-X Bridge.
Please refer to PCIe to PCI/PCI-X Bridge Specification, sec 5.2.3.2,
5.2.3.3 and 5.2.3.4.
Signed-off-by: leoliu-oc <leoliu-oc@...oxin.com>
---
include/uapi/linux/pci_regs.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index e5f558d964939..28e20c4d0afc3 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -800,6 +800,9 @@
#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */
#define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */
+#define PCI_ERR_UNCOR_MASK2 0x30 /* PCIe to PCI/PCI-X Bridge */
+#define PCI_ERR_UNCOR_SEVER2 0x34 /* PCIe to PCI/PCI-X Bridge */
+#define PCI_ERR_CAP2 0x38 /* PCIe to PCI/PCI-X Bridge */
/* Virtual Channel */
#define PCI_VC_PORT_CAP1 0x04
--
2.34.1
Powered by blists - more mailing lists