[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <acf1de10-d705-6b38-59fd-e2f7374f1e13@amd.com>
Date: Mon, 3 Jul 2023 21:16:18 -0500
From: Mario Limonciello <mario.limonciello@....com>
To: andy.shevchenko@...il.com
Cc: Basavaraj.Natikar@....com, Shyam-sundar.S-k@....com,
linus.walleij@...aro.org, npliashechnikov@...il.com,
nmschulte@...il.com, friedrich.vock@....de, dridri85@...il.com,
linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/4] pinctrl: amd: Unify debounce handling into
amd_pinconf_set()
On 7/3/23 16:33, andy.shevchenko@...il.com wrote:
> Fri, Jun 30, 2023 at 02:47:15PM -0500, Mario Limonciello kirjoitti:
>> Debounce handling is done in two different entry points in the driver.
>> Unify this to make sure that it's always handled the same.
>
> ...
>
>> -static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
>> - unsigned debounce)
>> +static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned offset,
>> + unsigned debounce)
>
> Side note: Are you going to fix unsigned --> unsigned int?
> The former is discouraged.
>
> ...
>
>> +out:
>
> out_unlock: ?
>
>> raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
>>
>> return ret;
>
Ack, thanks will adjust both.
Powered by blists - more mailing lists