linux-kernel - [RFC V2 PATCH 2/9] riscv: avoid missing prototypes warning

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Message-Id: <20230704140924.315594-3-cleger@rivosinc.com>
Date:   Tue,  4 Jul 2023 16:09:17 +0200
From:   Clément Léger <cleger@...osinc.com>
To:     Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>
Cc:     Clément Léger <cleger@...osinc.com>,
        Stafford Horne <shorne@...il.com>,
        Brian Cain <bcain@...cinc.com>,
        Kefeng Wang <wangkefeng.wang@...wei.com>,
        "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>,
        Michael Ellerman <mpe@...erman.id.au>,
        Sunil V L <sunilvl@...tanamicro.com>,
        Anup Patel <apatel@...tanamicro.com>,
        Atish Patra <atishp@...osinc.com>,
        Andrew Jones <ajones@...tanamicro.com>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Heiko Stuebner <heiko@...ech.de>, Guo Ren <guoren@...nel.org>,
        Alexandre Ghiti <alexghiti@...osinc.com>,
        Masahiro Yamada <masahiroy@...nel.org>,
        Xianting Tian <xianting.tian@...ux.alibaba.com>,
        Sia Jee Heng <jeeheng.sia@...rfivetech.com>,
        Li Zhengyu <lizhengyu3@...wei.com>,
        Jisheng Zhang <jszhang@...nel.org>,
        "Gautham R. Shenoy" <gautham.shenoy@....com>,
        Mark Rutland <mark.rutland@....com>,
        Peter Zijlstra <peterz@...radead.org>,
        Marc Zyngier <maz@...nel.org>,
        Björn Töpel <bjorn@...osinc.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        Evan Green <evan@...osinc.com>,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [RFC V2 PATCH 2/9] riscv: avoid missing prototypes warning

Declare handle_misaligned_store/load() functions in entry-common.h and
include that file in traps_misaligned.c file to avoid warnings.

Signed-off-by: Clément Léger <cleger@...osinc.com>
---
 arch/riscv/include/asm/entry-common.h | 3 +++
 arch/riscv/kernel/traps.c             | 2 --
 arch/riscv/kernel/traps_misaligned.c  | 1 +
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h
index 6e4dee49d84b..58e9e2976e1b 100644
--- a/arch/riscv/include/asm/entry-common.h
+++ b/arch/riscv/include/asm/entry-common.h
@@ -8,4 +8,7 @@
 void handle_page_fault(struct pt_regs *regs);
 void handle_break(struct pt_regs *regs);
 
+int handle_misaligned_load(struct pt_regs *regs);
+int handle_misaligned_store(struct pt_regs *regs);
+
 #endif /* _ASM_RISCV_ENTRY_COMMON_H */
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index 8c258b78c925..7fcaf2fd27a1 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -155,8 +155,6 @@ DO_ERROR_INFO(do_trap_load_misaligned,
 DO_ERROR_INFO(do_trap_store_misaligned,
 	SIGBUS, BUS_ADRALN, "Oops - store (or AMO) address misaligned");
 #else
-int handle_misaligned_load(struct pt_regs *regs);
-int handle_misaligned_store(struct pt_regs *regs);
 
 asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt_regs *regs)
 {
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index e7bfb33089c1..0cccac4822a8 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -12,6 +12,7 @@
 #include <asm/processor.h>
 #include <asm/ptrace.h>
 #include <asm/csr.h>
+#include <asm/entry-common.h>
 
 #define INSN_MATCH_LB			0x3
 #define INSN_MASK_LB			0x707f
-- 
2.40.1