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Message-Id: <20230704140924.315594-5-cleger@rivosinc.com>
Date: Tue, 4 Jul 2023 16:09:19 +0200
From: Clément Léger <cleger@...osinc.com>
To: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>
Cc: Clément Léger <cleger@...osinc.com>,
Stafford Horne <shorne@...il.com>,
Brian Cain <bcain@...cinc.com>,
Kefeng Wang <wangkefeng.wang@...wei.com>,
"Russell King (Oracle)" <rmk+kernel@...linux.org.uk>,
Michael Ellerman <mpe@...erman.id.au>,
Sunil V L <sunilvl@...tanamicro.com>,
Anup Patel <apatel@...tanamicro.com>,
Atish Patra <atishp@...osinc.com>,
Andrew Jones <ajones@...tanamicro.com>,
Conor Dooley <conor.dooley@...rochip.com>,
Heiko Stuebner <heiko@...ech.de>, Guo Ren <guoren@...nel.org>,
Alexandre Ghiti <alexghiti@...osinc.com>,
Masahiro Yamada <masahiroy@...nel.org>,
Xianting Tian <xianting.tian@...ux.alibaba.com>,
Sia Jee Heng <jeeheng.sia@...rfivetech.com>,
Li Zhengyu <lizhengyu3@...wei.com>,
Jisheng Zhang <jszhang@...nel.org>,
"Gautham R. Shenoy" <gautham.shenoy@....com>,
Mark Rutland <mark.rutland@....com>,
Peter Zijlstra <peterz@...radead.org>,
Marc Zyngier <maz@...nel.org>,
Björn Töpel <bjorn@...osinc.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Evan Green <evan@...osinc.com>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [RFC V2 PATCH 4/9] riscv: report perf event for misaligned fault
Add missing calls to account for misaligned fault event using
perf_sw_event().
Signed-off-by: Clément Léger <cleger@...osinc.com>
---
arch/riscv/kernel/traps_misaligned.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index 9daed7d756ae..804f6c5e0e44 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -6,6 +6,7 @@
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
+#include <linux/perf_event.h>
#include <linux/irq.h>
#include <linux/stringify.h>
@@ -294,6 +295,8 @@ int handle_misaligned_load(struct pt_regs *regs)
unsigned long addr = regs->badaddr;
int i, fp = 0, shift = 0, len = 0;
+ perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
+
if (get_insn(regs, epc, &insn))
return -1;
@@ -382,6 +385,8 @@ int handle_misaligned_store(struct pt_regs *regs)
unsigned long addr = regs->badaddr;
int i, len = 0;
+ perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
+
if (get_insn(regs, epc, &insn))
return -1;
--
2.40.1
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