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Message-Id: <20230704140924.315594-7-cleger@rivosinc.com>
Date: Tue, 4 Jul 2023 16:09:21 +0200
From: Clément Léger <cleger@...osinc.com>
To: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>
Cc: Clément Léger <cleger@...osinc.com>,
Stafford Horne <shorne@...il.com>,
Brian Cain <bcain@...cinc.com>,
Kefeng Wang <wangkefeng.wang@...wei.com>,
"Russell King (Oracle)" <rmk+kernel@...linux.org.uk>,
Michael Ellerman <mpe@...erman.id.au>,
Sunil V L <sunilvl@...tanamicro.com>,
Anup Patel <apatel@...tanamicro.com>,
Atish Patra <atishp@...osinc.com>,
Andrew Jones <ajones@...tanamicro.com>,
Conor Dooley <conor.dooley@...rochip.com>,
Heiko Stuebner <heiko@...ech.de>, Guo Ren <guoren@...nel.org>,
Alexandre Ghiti <alexghiti@...osinc.com>,
Masahiro Yamada <masahiroy@...nel.org>,
Xianting Tian <xianting.tian@...ux.alibaba.com>,
Sia Jee Heng <jeeheng.sia@...rfivetech.com>,
Li Zhengyu <lizhengyu3@...wei.com>,
Jisheng Zhang <jszhang@...nel.org>,
"Gautham R. Shenoy" <gautham.shenoy@....com>,
Mark Rutland <mark.rutland@....com>,
Peter Zijlstra <peterz@...radead.org>,
Marc Zyngier <maz@...nel.org>,
Björn Töpel <bjorn@...osinc.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Evan Green <evan@...osinc.com>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [RFC V2 PATCH 6/9] riscv: add support for SBI misalignment trap delegation
Add support for misalignment trap delegation by setting it with
SBI_EXT_FW_FEATURE SBI extension. This extension allows to control SBI
behavior by requesting to set them to specific value. In order to
implement prctl(PR_SET_UNALIGN, PR_UNALIGN_SIGBUS) behavior properly, we
need to let the kernel handle the misalignment error by itself.
Signed-off-by: Clément Léger <cleger@...osinc.com>
---
arch/riscv/include/asm/sbi.h | 11 +++++++++++
arch/riscv/kernel/sbi.c | 21 +++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 5b4a1bf5f439..c1b74c7d0d56 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -30,6 +30,7 @@ enum sbi_ext_id {
SBI_EXT_HSM = 0x48534D,
SBI_EXT_SRST = 0x53525354,
SBI_EXT_PMU = 0x504D55,
+ SBI_EXT_FW_FEATURE = 0x46574654,
/* Experimentals extensions must lie within this range */
SBI_EXT_EXPERIMENTAL_START = 0x08000000,
@@ -236,6 +237,16 @@ enum sbi_pmu_ctr_type {
/* Flags defined for counter stop function */
#define SBI_PMU_STOP_FLAG_RESET (1 << 0)
+/* SBI function IDs for FW feature extension */
+#define SBI_EXT_FW_FEATURE_SET 0x0
+#define SBI_EXT_FW_FEATURE_GET 0x1
+
+enum sbi_fw_features_t {
+ SBI_FW_FEATURE_MISALIGNED_DELEG = 0,
+
+ SBI_FW_FEATURE_MAX,
+};
+
#define SBI_SPEC_VERSION_DEFAULT 0x1
#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index c672c8ba9a2a..3be48791455a 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -494,6 +494,16 @@ int sbi_remote_hfence_vvma_asid(const struct cpumask *cpu_mask,
}
EXPORT_SYMBOL(sbi_remote_hfence_vvma_asid);
+static int sbi_fw_feature_set(enum sbi_fw_features_t feature, bool set)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_FW_FEATURE, SBI_EXT_FW_FEATURE_SET, feature,
+ set, 0, 0, 0, 0);
+
+ return sbi_err_map_linux_errno(ret.error);
+}
+
static void sbi_srst_reset(unsigned long type, unsigned long reason)
{
sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason,
@@ -624,6 +634,17 @@ void __init sbi_init(void)
sbi_srst_reboot_nb.priority = 192;
register_restart_handler(&sbi_srst_reboot_nb);
}
+ /*
+ * TODO: this will likely need to be updated when SBI extension
+ * is ratified
+ */
+ if ((sbi_spec_version >= sbi_mk_version(1, 0)) &&
+ (sbi_probe_extension(SBI_EXT_FW_FEATURE) > 0)) {
+ pr_info("SBI FW_FEATURE extension detected\n");
+ /* Request misaligned handling delegation */
+ sbi_fw_feature_set(SBI_FW_FEATURE_MISALIGNED_DELEG,
+ true);
+ }
} else {
__sbi_set_timer = __sbi_set_timer_v01;
__sbi_send_ipi = __sbi_send_ipi_v01;
--
2.40.1
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