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Message-ID: <a7b7df27-d49c-a6a7-46a0-47cc1098e644@linux.ibm.com>
Date:   Wed, 5 Jul 2023 13:57:05 +0200
From:   Laurent Dufour <ldufour@...ux.ibm.com>
To:     "Zhang, Rui" <rui.zhang@...el.com>,
        "linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>
Cc:     lkp <lkp@...el.com>, "npiggin@...il.com" <npiggin@...il.com>,
        "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
        "bp@...en8.de" <bp@...en8.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "christophe.leroy@...roup.eu" <christophe.leroy@...roup.eu>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "mpe@...erman.id.au" <mpe@...erman.id.au>,
        "linux-arch@...r.kernel.org" <linux-arch@...r.kernel.org>
Subject: Re: [PATCH v3 6/9] cpu/SMT: Allow enabling partial SMT states via
 sysfs



Le 05/07/2023 à 05:14, Zhang, Rui a écrit :
> On Thu, 2023-06-29 at 16:31 +0200, Laurent Dufour wrote:
>> @@ -2580,6 +2597,17 @@ static ssize_t control_show(struct device
>> *dev,
>>   {
>>          const char *state = smt_states[cpu_smt_control];
>>   
>> +#ifdef CONFIG_HOTPLUG_SMT
>> +       /*
>> +        * If SMT is enabled but not all threads are enabled then
>> show the
>> +        * number of threads. If all threads are enabled show "on".
>> Otherwise
>> +        * show the state name.
>> +        */
>> +       if (cpu_smt_control == CPU_SMT_ENABLED &&
>> +           cpu_smt_num_threads != cpu_smt_max_threads)
>> +               return sysfs_emit(buf, "%d\n", cpu_smt_num_threads);
>> +#endif
>> +
> 
> My understanding is that cpu_smt_control is always set to
> CPU_SMT_NOT_IMPLEMENTED when CONFIG_HOTPLUG_SMT is not set, so this
> ifdef is not necessary, right?

Hi Rui,

Indeed, cpu_smt_control, cpu_smt_num_threads and cpu_smt_max_threads are 
only defined when CONFIG_HOTPLUG_SMT is set. This is the reason for this 
#ifdef block.

This has been reported by the kernel test robot testing v2:
https://lore.kernel.org/oe-kbuild-all/202306282340.Ihqm0fLA-lkp@intel.com

Cheers,
Laurent.

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