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Message-ID: <9d5c1411-e56e-fa56-c8f2-808e0c403d9a@linaro.org>
Date: Thu, 6 Jul 2023 08:38:56 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Mrinmay Sarkar <quic_msarkar@...cinc.com>, agross@...nel.org,
andersson@...nel.org, krzysztof.kozlowski+dt@...aro.org,
conor+dt@...nel.org, konrad.dybcio@...aro.org, mani@...nel.org
Cc: quic_shazhuss@...cinc.com, quic_nitegupt@...cinc.com,
quic_ramkri@...cinc.com, quic_nayiluri@...cinc.com,
Bjorn Helgaas <bhelgaas@...gle.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Rob Herring <robh@...nel.org>, Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-phy@...ts.infradead.org
Subject: Re: [PATCH v1 6/6] arm64: dts: qcom: sa8775p-ride: enable pcie nodes
On 05/07/2023 10:17, Mrinmay Sarkar wrote:
> Enable pcie0, pcie1 nodes and their respective phy's.
>
> Signed-off-by: Mrinmay Sarkar <quic_msarkar@...cinc.com>
> ---
> arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 68 +++++++++++++++++++++++
> 1 file changed, 68 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> index ab767cfa51ff..4a39294259fe 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> @@ -443,6 +443,74 @@ qup_uart17_rx: qup0-uart17-rx-pins {
> bias-pull-down;
> };
> };
> +
> + pcie0_default_state: pcie0-default {
> + perst {
It does not look like you tested the DTS against bindings. Please run
`make dtbs_check` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
Best regards,
Krzysztof
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