lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <997780a9-1cbc-46a2-2743-7fd493682278@foss.st.com>
Date:   Thu, 6 Jul 2023 11:30:46 +0200
From:   Gatien CHEVALLIER <gatien.chevallier@...s.st.com>
To:     Alexandre TORGUE <alexandre.torgue@...s.st.com>,
        <Oleksii_Moisieiev@...m.com>, <gregkh@...uxfoundation.org>,
        <herbert@...dor.apana.org.au>, <davem@...emloft.net>,
        <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
        <conor+dt@...nel.org>, <vkoul@...nel.org>, <jic23@...nel.org>,
        <olivier.moysan@...s.st.com>, <arnaud.pouliquen@...s.st.com>,
        <mchehab@...nel.org>, <fabrice.gasnier@...s.st.com>,
        <andi.shyti@...nel.org>, <ulf.hansson@...aro.org>,
        <edumazet@...gle.com>, <kuba@...nel.org>, <pabeni@...hat.com>,
        <hugues.fruchet@...s.st.com>, <lee@...nel.org>, <will@...nel.org>,
        <catalin.marinas@....com>, <arnd@...nel.org>,
        <richardcochran@...il.com>
CC:     <linux-crypto@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-stm32@...md-mailman.stormreply.com>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <dmaengine@...r.kernel.org>,
        <linux-i2c@...r.kernel.org>, <linux-iio@...r.kernel.org>,
        <alsa-devel@...a-project.org>, <linux-media@...r.kernel.org>,
        <linux-mmc@...r.kernel.org>, <netdev@...r.kernel.org>,
        <linux-phy@...ts.infradead.org>, <linux-serial@...r.kernel.org>,
        <linux-spi@...r.kernel.org>, <linux-usb@...r.kernel.org>
Subject: Re: [PATCH 07/10] arm64: dts: st: add RIFSC as a domain controller
 for STM32MP25x boards

Hi Alex,

On 7/6/23 11:25, Alexandre TORGUE wrote:
> Hi Gatien
> 
> On 7/5/23 19:27, Gatien Chevallier wrote:
>> RIFSC is a firewall controller. Change its compatible so that is matches
>> the documentation and reference RIFSC as a feature-domain-controller.
>>
>> Signed-off-by: Gatien Chevallier <gatien.chevallier@...s.st.com>
>> ---
>>   arch/arm64/boot/dts/st/stm32mp251.dtsi | 5 ++++-
>>   1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi 
>> b/arch/arm64/boot/dts/st/stm32mp251.dtsi
>> index 5268a4321841..62101084cab8 100644
>> --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
>> +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
>> @@ -106,17 +106,20 @@ soc@0 {
>>           ranges = <0x0 0x0 0x0 0x80000000>;
>>           rifsc: rifsc-bus@...80000 {
>> -            compatible = "simple-bus";
>> +            compatible = "st,stm32mp25-rifsc";
> 
> You could keep "simple-bus" compatible (in second position). In case of 
> the RIFSC is not probed, the platform will be able to boot. If you agree 
> you can use the same for ETZPC.
> 
> Cheers
> Alex

Sure, good point.

I'll change that in V2

Best regards,
Gatien
> 
>>               reg = <0x42080000 0x1000>;
>>               #address-cells = <1>;
>>               #size-cells = <1>;
>>               ranges;
>> +            feature-domain-controller;
>> +            #feature-domain-cells = <1>;
>>               usart2: serial@...e0000 {
>>                   compatible = "st,stm32h7-uart";
>>                   reg = <0x400e0000 0x400>;
>>                   interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>                   clocks = <&ck_flexgen_08>;
>> +                feature-domains = <&rifsc 32>;
>>                   status = "disabled";
>>               };
>>           };
> 

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ