linux-kernel - Re: [PATCH v1 5/6] arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes

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Message-ID: <20230706111553.GB4808@thinkpad>
Date:   Thu, 6 Jul 2023 16:45:53 +0530
From:   Manivannan Sadhasivam <mani@...nel.org>
To:     Konrad Dybcio <konrad.dybcio@...aro.org>
Cc:     Mrinmay Sarkar <quic_msarkar@...cinc.com>, agross@...nel.org,
        andersson@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        conor+dt@...nel.org, quic_shazhuss@...cinc.com,
        quic_nitegupt@...cinc.com, quic_ramkri@...cinc.com,
        quic_nayiluri@...cinc.com,
        Lorenzo Pieralisi <lpieralisi@...nel.org>,
        Krzysztof Wilczyński <kw@...ux.com>,
        Rob Herring <robh@...nel.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Vinod Koul <vkoul@...nel.org>,
        Kishon Vijay Abraham I <kishon@...nel.org>,
        linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-phy@...ts.infradead.org
Subject: Re: [PATCH v1 5/6] arm64: dts: qcom: sa8775p: Add pcie0 and pcie1
 nodes

On Thu, Jul 06, 2023 at 12:01:37PM +0200, Konrad Dybcio wrote:
> On 5.07.2023 10:17, Mrinmay Sarkar wrote:
> > Add pcie dtsi nodes for two controllers found on sa8775p platform.
> > 
> > Signed-off-by: Mrinmay Sarkar <quic_msarkar@...cinc.com>
> > ---[...]
> 
> > +	pcie1_phy: phy@...4000 {
> > +		compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
> > +		reg = <0x0 0x1c14000 0x0 0x4000>;
> > +
> > +		clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
> > +			 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> > +			 <&gcc GCC_PCIE_CLKREF_EN>,
> > +			 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
> > +			 <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
> > +			 <&gcc GCC_PCIE_1_PIPE_CLK>,
> > +			 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
> > +
> > +		clock-names = "aux", "cfg_ahb", "ref", "rchng", "phy_aux",
> > +						"pipe", "pipediv2";
> > +
> > +		assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
> > +		assigned-clock-rates = <100000000>;
> > +
> > +		power-domains = <&gcc PCIE_1_GDSC>;
> Please check if it's the correct power domain. I've heard that the PCIe PHY
> may be hooked up to something else but have no way of confirming myself.
> 

Right, I missed it during my review. PHYs are powered by MX domain on all the
platforms I have seen so far, so this should be cross checked.

And someone should fix the existing dts.

- Mani

> Konrad
> > +
> > +		resets = <&gcc GCC_PCIE_1_PHY_BCR>;
> > +		reset-names = "phy";
> > +
> > +		#clock-cells = <0>;
> > +		clock-output-names = "pcie_1_pipe_clk";
> > +
> > +		#phy-cells = <0>;
> > +
> > +		status = "disabled";
> > +
> > +	};
> >  };

-- 
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