| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <0b5771b3-31b1-c17c-2be4-9b71538078bb@linaro.org>
Date: Sun, 9 Jul 2023 19:41:25 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Jishnu Prakash <quic_jprakash@...cinc.com>, agross@...nel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linus.walleij@...aro.org, Jonathan.Cameron@...wei.com,
sboyd@...nel.org, dmitry.baryshkov@...aro.org,
quic_subbaram@...cinc.com, quic_collinsd@...cinc.com,
quic_kamalw@...cinc.com, quic_jestar@...cinc.com,
marijn.suijten@...ainline.org, andriy.shevchenko@...ux.intel.com,
Jonathan Cameron <jic23@...nel.org>,
Lars-Peter Clausen <lars@...afoo.de>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Arnd Bergmann <arnd@...db.de>,
Cosmin Tanislav <demonsingur@...il.com>,
Mike Looijmans <mike.looijmans@...ic.nl>,
Ramona Bolboaca <ramona.bolboaca@...log.com>,
ChiYuan Huang <cy_huang@...htek.com>,
Ibrahim Tilki <Ibrahim.Tilki@...log.com>,
William Breathitt Gray <william.gray@...aro.org>,
Lee Jones <lee@...nel.org>,
Leonard Göhrs <l.goehrs@...gutronix.de>,
Haibo Chen <haibo.chen@....com>, linux-iio@...r.kernel.org,
linux-arm-msm@...r.kernel.org
Cc: linux-arm-msm-owner@...r.kernel.org
Subject: Re: [PATCH 07/11] iio: adc: Add support for QCOM PMIC5 Gen3 ADC
On 08/07/2023 09:28, Jishnu Prakash wrote:
> The ADC architecture on PMIC5 Gen3 is similar to that on PMIC5 Gen2,
> with all SW communication to ADC going through PMK8550 which
> communicates with other PMICs through PBS. One major difference is
> that the register interface used here is that of an SDAM present on
...
> +static int adc5_gen3_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct iio_dev *indio_dev;
> + struct adc5_chip *adc;
> + struct regmap *regmap;
> + int ret, i, irq;
> + u32 *reg;
> + char buf[20];
> +
> + regmap = dev_get_regmap(dev->parent, NULL);
> + if (!regmap)
> + return -ENODEV;
> +
> + indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
> + if (!indio_dev)
> + return -ENOMEM;
> +
> + adc = iio_priv(indio_dev);
> + adc->regmap = regmap;
> + adc->dev = dev;
> +
> + ret = device_property_count_u32(dev, "reg");
> + if (ret < 0)
> + return ret;
> +
> + adc->num_sdams = ret;
> +
> + reg = devm_kcalloc(dev, adc->num_sdams, sizeof(u32), GFP_KERNEL);
> + if (!reg)
> + return -ENOMEM;
> +
> + ret = device_property_read_u32_array(dev, "reg", reg, adc->num_sdams);
> + if (ret) {
> + dev_err(adc->dev, "Failed to read reg property, ret=%d\n", ret);
> + return ret;
> + }
> +
> + adc->base = devm_kcalloc(adc->dev, adc->num_sdams, sizeof(*adc->base), GFP_KERNEL);
> + if (!adc->base)
> + return -ENOMEM;
> +
> + for (i = 0; i < adc->num_sdams; i++) {
> + adc->base[i].base_addr = reg[i];
> +
> + irq = platform_get_irq(pdev, i);
> + if (irq < 0) {
> + dev_err(adc->dev, "Failed to get SDAM%d irq, ret=%d\n", i, irq);
> + return irq;
return dev_err_probe
> + }
> + adc->base[i].irq = irq;
> +
> + scnprintf(buf, sizeof(buf), "adc-sdam%d", i);
> + adc->base[i].irq_name = devm_kstrdup(adc->dev, buf, GFP_KERNEL);
> + if (!adc->base[i].irq_name)
> + return -ENOMEM;
> + }
> +
> + platform_set_drvdata(pdev, adc);
> +
> + init_completion(&adc->complete);
> + mutex_init(&adc->lock);
> +
> + ret = adc5_get_fw_data(adc);
> + if (ret < 0) {
> + dev_err(adc->dev, "adc get dt data failed, ret=%d\n", ret);
return dev_err_probe
> + return ret;
> + }
> +
> + for (i = 0; i < adc->num_sdams; i++) {
> + ret = devm_request_irq(dev, adc->base[i].irq, adc5_gen3_isr,
> + 0, adc->base[i].irq_name, adc);
> + if (ret < 0) {
> + dev_err(adc->dev, "Getting IRQ %d failed, ret=%d\n", adc->base[i].irq, ret);
return dev_err_probe
> + return ret;
> + }
> + }
> +
> + ret = adc_tm_register_tzd(adc);
> + if (ret < 0)
> + return ret;
> +
> + if (adc->n_tm_channels)
> + INIT_WORK(&adc->tm_handler_work, tm_handler_work);
> +
> + indio_dev->name = pdev->name;
> + indio_dev->modes = INDIO_DIRECT_MODE;
> + indio_dev->info = &adc5_gen3_info;
> + indio_dev->channels = adc->iio_chans;
> + indio_dev->num_channels = adc->nchannels;
> +
> + return devm_iio_device_register(dev, indio_dev);
> +}
> +
> +static int adc5_gen3_exit(struct platform_device *pdev)
> +{
> + struct adc5_chip *adc = platform_get_drvdata(pdev);
> + u8 data = 0;
> + int i, sdam_index;
> +
> + mutex_lock(&adc->lock);
> + /* Disable all available channels */
> + for (i = 0; i < adc->num_sdams * 8; i++) {
> + sdam_index = i / 8;
> + data = MEAS_INT_DISABLE;
> + adc5_gen3_write(adc, sdam_index, ADC5_GEN3_TIMER_SEL, &data, 1);
> +
> + /* To indicate there is an actual conversion request */
> + data = ADC5_GEN3_CHAN_CONV_REQ | (i - (sdam_index * 8));
> + adc5_gen3_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &data, 1);
> +
> + data = ADC5_GEN3_CONV_REQ_REQ;
> + adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &data, 1);
> + }
> +
> + mutex_unlock(&adc->lock);
> +
> + if (adc->n_tm_channels)
> + cancel_work_sync(&adc->tm_handler_work);
> +
> + return 0;
> +}
> +
> +static struct platform_driver adc5_gen3_driver = {
> + .driver = {
> + .name = "qcom-spmi-adc5-gen3",
> + .of_match_table = adc5_match_table,
> + },
> + .probe = adc5_gen3_probe,
> + .remove = adc5_gen3_exit,
> +};
> +module_platform_driver(adc5_gen3_driver);
> +
> +MODULE_ALIAS("platform:qcom-spmi-adc5-gen3");
Drop alias. If you need it, it means you screwed ID tables or your DTS.
Best regards,
Krzysztof
Powered by blists - more mailing lists