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Message-ID: <CAMuHMdWEYfBS8018BsVnYRj0+2VMY2QWnZnBB+ATfKPuAuJmMA@mail.gmail.com>
Date: Mon, 10 Jul 2023 16:21:23 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Magnus Damm <magnus.damm@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Linus Walleij <linus.walleij@...aro.org>,
linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-gpio@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [RFC PATCH 4/4] riscv: dts: renesas: r9a07g043f: Update
gpio-ranges property
Hi Prabhakar,
On Fri, Jun 30, 2023 at 2:05 PM Prabhakar <prabhakar.csengg@...il.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> On RZ/Five we have additional pins compared to the RZ/G2UL SoC so update
> the gpio-ranges property in RZ/Five SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Thanks for your patch!
> --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> @@ -42,6 +42,10 @@ cpu0_intc: interrupt-controller {
> };
> };
>
> +&pinctrl {
> + gpio-ranges = <&pinctrl 0 0 232>;
Is that correct? You only have 32 more pins than on r9a07g043u,
which uses:
gpio-ranges = <&pinctrl 0 0 152>;
> +};
> +
> &soc {
> dma-noncoherent;
> interrupt-parent = <&plic>;
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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