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Message-ID: <CAMRc=McCKW6x_qrYFowfuxZ8O3at1NjudjyxabHTomzQz7R0yg@mail.gmail.com>
Date: Mon, 10 Jul 2023 11:04:57 +0200
From: Bartosz Golaszewski <brgl@...ev.pl>
To: Huqiang Qin <huqiang.qin@...ogic.com>
Cc: linus.walleij@...aro.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
neil.armstrong@...aro.org, khilman@...libre.com,
jbrunet@...libre.com, martin.blumenstingl@...glemail.com,
andy@...nel.org, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-amlogic@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH V2 1/2] dt-bindings: gpio: Add a header file for Amlogic
C3 SoCs
On Mon, Jul 10, 2023 at 6:28 AM Huqiang Qin <huqiang.qin@...ogic.com> wrote:
>
> Add dt-binding and related header file for Amlogic C3 GPIO.
>
The subject of this patch is describing the new model, not only adding
the header, so make the commit message say that, e.g.: dt-bindings:
...: describe xyz
Bart
> Signed-off-by: Huqiang Qin <huqiang.qin@...ogic.com>
> ---
> .../pinctrl/amlogic,meson-pinctrl-a1.yaml | 1 +
> include/dt-bindings/gpio/amlogic-c3-gpio.h | 72 +++++++++++++++++++
> 2 files changed, 73 insertions(+)
> create mode 100644 include/dt-bindings/gpio/amlogic-c3-gpio.h
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml
> index 99080c9eaac3..e019b6aa6ca3 100644
> --- a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml
> @@ -17,6 +17,7 @@ properties:
> enum:
> - amlogic,meson-a1-periphs-pinctrl
> - amlogic,meson-s4-periphs-pinctrl
> + - amlogic,c3-periphs-pinctrl
>
> required:
> - compatible
> diff --git a/include/dt-bindings/gpio/amlogic-c3-gpio.h b/include/dt-bindings/gpio/amlogic-c3-gpio.h
> new file mode 100644
> index 000000000000..75c8da6f505f
> --- /dev/null
> +++ b/include/dt-bindings/gpio/amlogic-c3-gpio.h
> @@ -0,0 +1,72 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> +/*
> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
> + * Author: Huqiang Qin <huqiang.qin@...ogic.com>
> + */
> +
> +#ifndef _DT_BINDINGS_AMLOGIC_C3_GPIO_H
> +#define _DT_BINDINGS_AMLOGIC_C3_GPIO_H
> +
> +#define GPIOE_0 0
> +#define GPIOE_1 1
> +#define GPIOE_2 2
> +#define GPIOE_3 3
> +#define GPIOE_4 4
> +
> +#define GPIOB_0 5
> +#define GPIOB_1 6
> +#define GPIOB_2 7
> +#define GPIOB_3 8
> +#define GPIOB_4 9
> +#define GPIOB_5 10
> +#define GPIOB_6 11
> +#define GPIOB_7 12
> +#define GPIOB_8 13
> +#define GPIOB_9 14
> +#define GPIOB_10 15
> +#define GPIOB_11 16
> +#define GPIOB_12 17
> +#define GPIOB_13 18
> +#define GPIOB_14 19
> +
> +#define GPIOC_0 20
> +#define GPIOC_1 21
> +#define GPIOC_2 22
> +#define GPIOC_3 23
> +#define GPIOC_4 24
> +#define GPIOC_5 25
> +#define GPIOC_6 26
> +
> +#define GPIOX_0 27
> +#define GPIOX_1 28
> +#define GPIOX_2 29
> +#define GPIOX_3 30
> +#define GPIOX_4 31
> +#define GPIOX_5 32
> +#define GPIOX_6 33
> +#define GPIOX_7 34
> +#define GPIOX_8 35
> +#define GPIOX_9 36
> +#define GPIOX_10 37
> +#define GPIOX_11 38
> +#define GPIOX_12 39
> +#define GPIOX_13 40
> +
> +#define GPIOD_0 41
> +#define GPIOD_1 42
> +#define GPIOD_2 43
> +#define GPIOD_3 44
> +#define GPIOD_4 45
> +#define GPIOD_5 46
> +#define GPIOD_6 47
> +
> +#define GPIOA_0 48
> +#define GPIOA_1 49
> +#define GPIOA_2 50
> +#define GPIOA_3 51
> +#define GPIOA_4 52
> +#define GPIOA_5 53
> +
> +#define GPIO_TEST_N 54
> +
> +#endif /* _DT_BINDINGS_AMLOGIC_C3_GPIO_H */
> --
> 2.37.1
>
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