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Message-ID: <20230710025834.20513-1-allen-kh.cheng@mediatek.com>
Date: Mon, 10 Jul 2023 10:58:34 +0800
From: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
To: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Conor Dooley <conor+dt@...nel.org>
CC: <Project_Global_Chrome_Upstream_Group@...iatek.com>,
<angelogioacchino.delregno@...labora.com>,
<devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>,
Allen-KH Cheng <allen-kh.cheng@...iatek.com>
Subject: [PATCH] arm64: dts: mediatek: mt8192: Add SVS node
Add MediaTek Smart Voltage Scaling (SVS) node for MT8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 5e94cb4aeb44..0131cfefc0a1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -790,6 +790,18 @@
status = "disabled";
};
+ svs: svs@...0b000 {
+ compatible = "mediatek,mt8192-svs";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_THERM>;
+ clock-names = "main";
+ nvmem-cells = <&svs_calibration>, <&lvts_e_data1>;
+ nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
+ resets = <&infracfg MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST>;
+ reset-names = "svs_rst";
+ };
+
pwm0: pwm@...0e000 {
compatible = "mediatek,mt8183-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
--
2.18.0
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