linux-kernel - Re: [PATCH] arm64: zynqmp: Assign TSU clock frequency for GEMs

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Message-ID: <bc160892-6b84-fe20-ec6a-a3f9f7faef11@amd.com>
Date:   Mon, 10 Jul 2023 12:06:10 +0200
From:   Michal Simek <michal.simek@....com>
To:     linux-kernel@...r.kernel.org, monstr@...str.eu,
        michal.simek@...inx.com, git@...inx.com
Cc:     Harini Katakam <harini.katakam@....com>, Andrew Davis <afd@...com>,
        Ashok Reddy Soma <ashok.reddy.soma@...inx.com>,
        Conor Dooley <conor+dt@...nel.org>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Laurent Pinchart <laurent.pinchart@...asonboard.com>,
        Manikanta Guntupalli <manikanta.guntupalli@....com>,
        Parth Gajjar <parth.gajjar@....com>,
        Rob Herring <robh+dt@...nel.org>,
        Robert Hancock <robert.hancock@...ian.com>,
        Vishal Sagar <vishal.sagar@....com>,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH] arm64: zynqmp: Assign TSU clock frequency for GEMs



On 6/8/23 14:51, Michal Simek wrote:
> From: Harini Katakam <harini.katakam@....com>
> 
> Allow changing TSU clock for all GEMs. Kria SOM is using this
> functionality that's why set TSU clock frequency as 250MHz (minimum when
> running at 1G) to allow PTP functionality.
> 
> Signed-off-by: Harini Katakam <harini.katakam@....com>
> Signed-off-by: Michal Simek <michal.simek@....com>
> ---
> 
>   arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi       | 4 ++++
>   arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 1 +
>   arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 1 +
>   3 files changed, 6 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> index f04716841a0c..ccaca29200bb 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> @@ -146,24 +146,28 @@ &gem0 {
>   	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
>   		 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
>   		 <&zynqmp_clk GEM_TSU>;
> +	assigned-clocks = <&zynqmp_clk GEM_TSU>;
>   };
>   
>   &gem1 {
>   	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
>   		 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
>   		 <&zynqmp_clk GEM_TSU>;
> +	assigned-clocks = <&zynqmp_clk GEM_TSU>;
>   };
>   
>   &gem2 {
>   	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
>   		 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
>   		 <&zynqmp_clk GEM_TSU>;
> +	assigned-clocks = <&zynqmp_clk GEM_TSU>;
>   };
>   
>   &gem3 {
>   	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
>   		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
>   		 <&zynqmp_clk GEM_TSU>;
> +	assigned-clocks = <&zynqmp_clk GEM_TSU>;
>   };
>   
>   &gpio {
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> index e06c6824dea4..ae1b9b2bdbee 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> @@ -145,6 +145,7 @@ &gem3 { /* required by spec */
>   	pinctrl-0 = <&pinctrl_gem3_default>;
>   	phy-handle = <&phy0>;
>   	phy-mode = "rgmii-id";
> +	assigned-clock-rates = <250000000>;
>   
>   	mdio: mdio {
>   		#address-cells = <1>;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> index 030e2c93f0e6..b59e48be6465 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> @@ -128,6 +128,7 @@ &gem3 { /* required by spec */
>   	pinctrl-0 = <&pinctrl_gem3_default>;
>   	phy-handle = <&phy0>;
>   	phy-mode = "rgmii-id";
> +	assigned-clock-rates = <250000000>;
>   
>   	mdio: mdio {
>   		#address-cells = <1>;

Applied.
M