[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <5cf15f85-0397-96f7-4110-13494551b53b@quicinc.com>
Date: Tue, 11 Jul 2023 12:02:22 +0800
From: "Aiqun(Maria) Yu" <quic_aiquny@...cinc.com>
To: Will Deacon <will@...nel.org>
CC: <corbet@....net>, <catalin.marinas@....com>, <maz@...nel.org>,
<quic_pkondeti@...cinc.com>, <quic_kaushalk@...cinc.com>,
<quic_satyap@...cinc.com>, <quic_shashim@...cinc.com>,
<quic_songxue@...cinc.com>, <linux-doc@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH] arm64: Add the arm64.nolse_atomics command line option
On 7/10/2023 5:37 PM, Will Deacon wrote:
> On Mon, Jul 10, 2023 at 01:59:55PM +0800, Maria Yu wrote:
>> In order to be able to disable lse_atomic even if cpu
>> support it, most likely because of memory controller
>> cannot deal with the lse atomic instructions, use a
>> new idreg override to deal with it.
>
> This should not be a problem for cacheable memory though, right?
>
> Given that Linux does not issue atomic operations to non-cacheable mappings,
> I'm struggling to see why there's a problem here.
The lse atomic operation can be issued on non-cacheable mappings as
well. Even if it is cached data, with different CPUECTLR_EL1 setting, it
can also do far lse atomic operations.
>
> Please can you explain the problem that you are trying to solve?
In our current case, it is a 100% reproducible issue that happened for
uncached data, the cpu which support LSE atomic, but the system's DDR
subsystem is not support this and caused a NOC error and thus
synchronous external abort happened.
>
> Will
--
Thx and BRs,
Aiqun(Maria) Yu
Powered by blists - more mailing lists