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Message-ID: <ac95ffd2-50c6-f715-5c37-f658bacf4ca4@ti.com>
Date: Tue, 11 Jul 2023 11:46:01 +0530
From: "Verma, Achal" <a-verma1@...com>
To: Li Chen <me@...ux.beauty>, Vignesh Raghavendra <vigneshr@...com>,
Tom Joseph <tjoseph@...ence.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Rob Herring <robh@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
linux-omap <linux-omap@...r.kernel.org>,
linux-pci <linux-pci@...r.kernel.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/2] PCI: j721e: Allow async probe
On 7/7/2023 7:53 AM, Li Chen wrote:
> From: Li Chen <lchen@...arella.com>
>
> I observed that on Ambarella SoC, which also utilizes
> the Cadence controller, the boot time increases by 1
> second when no endpoints (including switch) are connected
> to PCIe. This increase is caused by cdns_pcie_host_wait_for_link.
>
> Enabling async probe can eliminate this boot time increase.
>
> I guess j721e also has this issue.
I have tested this along with:
https://lore.kernel.org
/all/1892e2ae15f.f7e5dc061620757.4339091752690983066@...ux.beauty/
But I couldn't find second patch in this series.
>
> Signed-off-by: Li Chen <lchen@...arella.com>
Tested-by: Achal Verma <a-verma1@...com>
> ---
> drivers/pci/controller/cadence/pci-j721e.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index e70213c9060a..660c13bdb606 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -561,6 +561,7 @@ static struct platform_driver j721e_pcie_driver = {
> .name = "j721e-pcie",
> .of_match_table = of_j721e_pcie_match,
> .suppress_bind_attrs = true,
> + .probe_type = PROBE_PREFER_ASYNCHRONOUS,
> },
> };
> builtin_platform_driver(j721e_pcie_driver);
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