linux-kernel - Re: [PATCH 0/4] riscv: tlb flush improvements

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Message-ID: <20230712-frying-unaired-e3acb5150e8b@spud>
Date:   Wed, 12 Jul 2023 18:19:47 +0100
From:   Conor Dooley <conor@...nel.org>
To:     Alexandre Ghiti <alex@...ti.fr>
Cc:     Conor Dooley <conor.dooley@...rochip.com>,
        Alexandre Ghiti <alexghiti@...osinc.com>,
        Will Deacon <will@...nel.org>,
        "Aneesh Kumar K . V" <aneesh.kumar@...ux.ibm.com>,
        Andrew Morton <akpm@...ux-foundation.org>,
        Nick Piggin <npiggin@...il.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Mayuresh Chitale <mchitale@...tanamicro.com>,
        Vincent Chen <vincent.chen@...ive.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>, linux-arch@...r.kernel.org,
        linux-mm@...ck.org, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 0/4] riscv: tlb flush improvements

On Wed, Jul 12, 2023 at 05:18:00PM +0200, Alexandre Ghiti wrote:
> On 12/07/2023 09:08, Conor Dooley wrote:
> > On Tue, Jul 11, 2023 at 09:54:30AM +0200, Alexandre Ghiti wrote:
> > > This series optimizes the tlb flushes on riscv which used to simply
> > > flush the whole tlb whatever the size of the range to flush or the size
> > > of the stride.
> > > 
> > > Patch 3 introduces a threshold that is microarchitecture specific and
> > > will very likely be modified by vendors, not sure though which mechanism
> > > we'll use to do that (dt? alternatives? vendor initialization code?).
> 
> 
> @Conor any idea how to achieve this?

It's in my queue of things to look at, just been prioritising the
extension related stuff the last few days. Hopefully I'll have a chance
to think about this tomorrow.. Famous last words probably.

> > > Next steps would be to implement:
> > > - svinval extension as Mayuresh did here [1]
> > > - BATCHED_UNMAP_TLB_FLUSH (I'll wait for arm64 patchset to land)
> > > - MMU_GATHER_RCU_TABLE_FREE
> > > - MMU_GATHER_MERGE_VMAS
> > > 
> > > Any other idea welcome.
> > > 
> > > [1] https://lore.kernel.org/linux-riscv/20230623123849.1425805-1-mchitale@ventanamicro.com/
> > > 
> > > Alexandre Ghiti (4):
> > >    riscv: Improve flush_tlb()
> > >    riscv: Improve flush_tlb_range() for hugetlb pages
> > >    riscv: Make __flush_tlb_range() loop over pte instead of flushing the
> > >      whole tlb
> > The whole series does not build on nommu & this one adds a build warning
> > for regular builds:
> > +      1 ../arch/riscv/mm/tlbflush.c:32:15: warning: symbol 'tlb_flush_all_threshold' was not declared. Should it be static?
> > 
> > Cheers,
> > Conor.
> 
> 
> I'll fix the nommu build, sorry about that. Weird I missed this warning,
> that's an LLVM build right? That variable will need to overwritten by the
> vendors, so that should not be static (but it will depend on what solution
> we implement).

Just make it static until we actually have a vendor implementation of
this stuff please, since we don't know what that will look like yet.

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