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Message-Id: <20230713204932.1591255-1-Frank.Li@nxp.com>
Date: Thu, 13 Jul 2023 16:49:29 -0400
From: Frank Li <Frank.Li@....com>
To: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
NXP Linux Team <linux-imx@....com>,
Peng Fan <peng.fan@....com>, Chester Lin <clin@...e.com>,
Li Yang <leoyang.li@....com>, Zhou Peng <eagle.zhou@....com>,
Pierre Gondois <pierre.gondois@....com>,
devicetree@...r.kernel.org (open list:OPEN FIRMWARE AND FLATTENED
DEVICE TREE BINDINGS),
linux-arm-kernel@...ts.infradead.org (moderated list:ARM/FREESCALE IMX
/ MXC ARM ARCHITECTURE), linux-kernel@...r.kernel.org (open list)
Cc: imx@...ts.linux.dev
Subject: [PATCH v2 1/3] arm64: dts: imx8qm: add cpu frequency table
Add A53 and A72 opp_table.
Reviewed-by: Peng Fan <peng.fan@....com>
Signed-off-by: Frank Li <Frank.Li@....com>
---
change from v1 to v2
- pass make dtbs_check
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 72 +++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 9fff867709f0..effd84ebade1 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -62,6 +62,7 @@ A53_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
+ clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
@@ -70,12 +71,14 @@ A53_0: cpu@0 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
};
A53_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
+ clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
@@ -84,12 +87,14 @@ A53_1: cpu@1 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
};
A53_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
+ clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
@@ -98,12 +103,14 @@ A53_2: cpu@2 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
};
A53_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
+ clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
@@ -112,12 +119,14 @@ A53_3: cpu@3 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
};
A72_0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x100>;
+ clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>;
enable-method = "psci";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
@@ -126,14 +135,17 @@ A72_0: cpu@100 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&A72_L2>;
+ operating-points-v2 = <&a72_opp_table>;
};
A72_1: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x101>;
+ clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>;
enable-method = "psci";
next-level-cache = <&A72_L2>;
+ operating-points-v2 = <&a72_opp_table>;
};
A53_L2: l2-cache0 {
@@ -155,6 +167,66 @@ A72_L2: l2-cache1 {
};
};
+ a53_opp_table: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-896000000 {
+ opp-hz = /bits/ 64 <896000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-1104000000 {
+ opp-hz = /bits/ 64 <1104000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+ };
+
+ a72_opp_table: opp-table-1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-1596000000 {
+ opp-hz = /bits/ 64 <1596000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+ };
+
gic: interrupt-controller@...00000 {
compatible = "arm,gic-v3";
reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
--
2.34.1
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