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Message-ID: <20230713083101.971525-2-quic_ipkumar@quicinc.com>
Date: Thu, 13 Jul 2023 14:01:01 +0530
From: Praveenkumar I <quic_ipkumar@...cinc.com>
To: <agross@...nel.org>, <andersson@...nel.org>,
<konrad.dybcio@...aro.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
<linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
CC: <quic_varada@...cinc.com>
Subject: [PATCH 1/1] arm64: dts: qcom: ipq9574: Add cpu cooling maps
Add cpu cooling maps for passive trip points. The cpu cooling
device states are mapped to cpufreq based scaling frequencies.
Signed-off-by: Praveenkumar I <quic_ipkumar@...cinc.com>
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 61 +++++++++++++++++++++++----
1 file changed, 53 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index f120c7c52351..45b24c7d5ac3 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@@ -42,6 +43,7 @@ CPU0: cpu@0 {
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
+ #cooling-cells = <2>;
};
CPU1: cpu@1 {
@@ -54,6 +56,7 @@ CPU1: cpu@1 {
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
+ #cooling-cells = <2>;
};
CPU2: cpu@2 {
@@ -66,6 +69,7 @@ CPU2: cpu@2 {
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
+ #cooling-cells = <2>;
};
CPU3: cpu@3 {
@@ -78,6 +82,7 @@ CPU3: cpu@3 {
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
+ #cooling-cells = <2>;
};
L2_0: l2-cache {
@@ -727,18 +732,28 @@ cpu0-thermal {
thermal-sensors = <&tsens 10>;
trips {
- cpu-critical {
+ cpu0_crit: cpu-critical {
temperature = <120000>;
hysteresis = <10000>;
type = "critical";
};
- cpu-passive {
+ cpu0_alert: cpu-passive {
temperature = <110000>;
hysteresis = <1000>;
type = "passive";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu0_alert>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu1-thermal {
@@ -747,18 +762,28 @@ cpu1-thermal {
thermal-sensors = <&tsens 11>;
trips {
- cpu-critical {
+ cpu1_crit: cpu-critical {
temperature = <120000>;
hysteresis = <10000>;
type = "critical";
};
- cpu-passive {
+ cpu1_alert: cpu-passive {
temperature = <110000>;
hysteresis = <1000>;
type = "passive";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu1_alert>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu2-thermal {
@@ -767,18 +792,28 @@ cpu2-thermal {
thermal-sensors = <&tsens 12>;
trips {
- cpu-critical {
+ cpu2_crit: cpu-critical {
temperature = <120000>;
hysteresis = <10000>;
type = "critical";
};
- cpu-passive {
+ cpu2_alert: cpu-passive {
temperature = <110000>;
hysteresis = <1000>;
type = "passive";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu2_alert>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu3-thermal {
@@ -787,18 +822,28 @@ cpu3-thermal {
thermal-sensors = <&tsens 13>;
trips {
- cpu-critical {
+ cpu3_crit: cpu-critical {
temperature = <120000>;
hysteresis = <10000>;
type = "critical";
};
- cpu-passive {
+ cpu3_alert: cpu-passive {
temperature = <110000>;
hysteresis = <1000>;
type = "passive";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu3_alert>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
wcss-phyb-thermal {
--
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