linux-kernel - i.MX8MP EQOS + 10/100MBit RMII Phy Issue

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Date:   Thu, 13 Jul 2023 12:27:35 +0200
From:   Marco Felsch <m.felsch@...gutronix.de>
To:     linux-imx@....com, festevam@...il.com, shawnguo@...nel.org,
        peppe.cavallaro@...com, alexandre.torgue@...s.st.com,
        joabreu@...opsys.com, mcoquelin.stm32@...il.com
Cc:     netdev@...r.kernel.org, linux-stm32@...md-mailman.stormreply.com,
        linux-kernel@...r.kernel.org, kernel@...gutronix.de
Subject: i.MX8MP EQOS + 10/100MBit RMII Phy Issue

Hi all,

I currently debug an issue regarding the i.MX8MP EQOS in combination
with an 10/100Mbit RMII phy. The phy supplies the 50MHz rmii-refclk and
is working in 100Mbit but stops working in 10Mbit mode.

While my debugging session I found a great IP core signal overview from
STM [1]. The ETH signals matches the ones also listed in the i.MX8MP
refernce manual, therefore I think that the NXP used IP core version
does match the STM one very well.

As seen in the overview [1] the SoC has to provide the correct rx/tx
clocks to the EQOS core which depends on the speed (10/100/1000) and the
interface (mii, rmii, rgmii). The clock selection can be done by the
mac_speed_o[1:0] signals or have to be done separatly via software _but_
it have to be done outside the EQOS IP core.

The NXP i.MX8MP RM has some integration registers layed within the
IOMUXC_GPR1 register to select the interface (MII/RGMII/MII) but no bits
to select correct speed.

Since the RMII 100Mbit case is working I now assume:
 1) NXP has a /2 predivider but no /20 predivder nor a mux to select
    between both. Is this correct?
 2) NXP has all dividers and muxes but did not document these. If so can
    you provide us the registers and bits?

I look forward to here from NXP :)

Regards,
  Marco

PS: - I also checked the Rockchip refernce manual and they do have
      proper clock dividers and muxes like STM.
    - I did test the 10Mbit case on the i.MX8MP-EVK as well which does
      work because they use a RGMII interface which does have a
      different clock handling.

[1] https://community.st.com/t5/stm32-mpus/faq-stm32mp1-how-to-configure-ethernet-phy-clocks/ta-p/49266; figure 83