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Message-ID: <19ad986d-7121-7b2b-40e6-5046917d5dfc@linaro.org>
Date: Sat, 15 Jul 2023 17:07:15 +0200
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Krishna chaitanya chundru <quic_krichai@...cinc.com>,
manivannan.sadhasivam@...aro.org
Cc: helgaas@...nel.org, linux-pci@...r.kernel.org,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
quic_vbadigan@...cinc.com, quic_nitegupt@...cinc.com,
quic_skananth@...cinc.com, quic_ramkri@...cinc.com,
krzysztof.kozlowski@...aro.org, Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>
Subject: Re: [PATCH v8 2/3] arm: dts: qcom: sdx65: Add PCIe interconnect path
On 13.07.2023 13:20, Krishna chaitanya chundru wrote:
> Add pcie-mem interconnect path to sdx65 platform.
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
> ---
No CPU - SLAVE_PCIE_0?
Konrad
> arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
> index 1a35830..77fa97c 100644
> --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
> @@ -332,6 +332,9 @@
> <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "global", "doorbell";
>
> + interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
> + interconnect-names = "pcie-mem";
> +
> resets = <&gcc GCC_PCIE_BCR>;
> reset-names = "core";
>
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