lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <db6ba884-7125-c2bb-de65-83b2f980e7a1@gmail.com>
Date:   Sun, 16 Jul 2023 10:03:30 +0800
From:   Guiting Shen <aarongt.shen@...il.com>
To:     Uwe Kleine-König <u.kleine-koenig@...gutronix.de>
Cc:     claudiu.beznea@...rochip.com, thierry.reding@...il.com,
        nicolas.ferre@...rochip.com, alexandre.belloni@...tlin.com,
        linux-arm-kernel@...ts.infradead.org, linux-pwm@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5] pwm: atmel: Enable clk when pwm already enabled in
 bootloader



On Sat,Jul 15,2023 at 20:12:53PM GMT+8, Uwe Kleine-König wrote:
> On Sat, Jul 15, 2023 at 10:36:53AM +0800, Guiting Shen wrote:
>> The driver would never call clk_enable() if the PWM channel was already
>> enabled in bootloader which lead to dump the warning message "the PWM
>> clock already disabled" when turning off the PWM channel.
>>
>> Add atmel_pwm_enable_clk_if_on() in probe function to enable clock if
>> the PWM channel was already enabled in bootloader.
>>
>> Signed-off-by: Guiting Shen <aarongt.shen@...il.com>
>> ---
>>   drivers/pwm/pwm-atmel.c | 50 +++++++++++++++++++++++++++++++++++++++--
>>   1 file changed, 48 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
>> index cdbc23649032..4dd6e1319343 100644
>> --- a/drivers/pwm/pwm-atmel.c
>> +++ b/drivers/pwm/pwm-atmel.c
>> @@ -36,7 +36,7 @@
>>   #define PWM_SR			0x0C
>>   #define PWM_ISR			0x1C
>>   /* Bit field in SR */
>> -#define PWM_SR_ALL_CH_ON	0x0F
>> +#define PWM_SR_ALL_CH_MASK	0x0F
>>   
>>   /* The following register is PWM channel related registers */
>>   #define PWM_CH_REG_OFFSET	0x200
>> @@ -464,6 +464,45 @@ static const struct of_device_id atmel_pwm_dt_ids[] = {
>>   };
>>   MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
>>   
>> +static int atmel_pwm_enable_clk_if_on(struct atmel_pwm_chip *atmel_pwm, bool on)
>> +{
>> +	unsigned int i, cnt = 0;
>> +	int ret = 0;
>> +	u32 sr;
>> +
>> +	sr = atmel_pwm_readl(atmel_pwm, PWM_SR) & PWM_SR_ALL_CH_MASK;
>> +	if (!sr)
>> +		return 0;
>> +
>> +	for (i = 0; i < atmel_pwm->chip.npwm; i++) {
>> +		if (sr & (1 << i))
>> +			cnt++;
>> +	}
> 
> If it's just about counting the set bits, there is the function
> bitmap_weight().

Got it, Thank you.


>> +	if (!on)
>> +		goto disable_clk;
>> +
>> +	for (i = 0; i < cnt; i++) {
>> +		ret = clk_enable(atmel_pwm->clk);
>> +		if (ret) {
>> +			dev_err(atmel_pwm->chip.dev,
>> +				"failed to enable clock for pwm #%d: %pe\n",
>> +							i, ERR_PTR(ret));
> 
> The output is bogus here. If SR is say 0xc, and the second enable
> fails, it's about pwm #3, but then i is 1.

I would just output the error clock message like this to fix it:
	dev_err(atmel_pwm->chip.dev,
		"failed to enable clock for pwm %pe\n", ERR_PTR(ret));


>> +			cnt = i;
>> +			goto disable_clk;
>> +		}
>> +	}
>> +
>> +	return 0;
>> +
>> +disable_clk:
>> +	while (cnt--)
>> +		clk_disable(atmel_pwm->clk);
>> +
>> +	return ret;
>> +}
>> +
>>   static int atmel_pwm_probe(struct platform_device *pdev)
>>   {
>>   	struct atmel_pwm_chip *atmel_pwm;
> 
> Best regards
> Uwe
> 

-- 
Best regards,
Guiting Shen

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ