linux-kernel - Re: [RESEND] clk: qcom: rcg: Update rcg configuration before enabling it

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Date:   Mon, 17 Jul 2023 14:48:55 -0500
From:   Andrew Halaney <ahalaney@...hat.com>
To:     Satya Priya Kakitapalli <quic_skakitap@...cinc.com>
Cc:     Konrad Dybcio <konrad.dybcio@...aro.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Jagadeesh Kona <quic_jkona@...cinc.com>,
        Taniya Das <quic_tdas@...cinc.com>
Subject: Re: [RESEND] clk: qcom: rcg: Update rcg configuration before
 enabling it

On Wed, Jul 12, 2023 at 07:18:12AM +0530, Satya Priya Kakitapalli wrote:
> From: Taniya Das <quic_tdas@...cinc.com>
> 
> If rcg is in disabled state when clk_rcg2_shared_set_rate is called, the
> new configuration is written to the configuration register but it won't be
> effective in h/w yet because update bit won't be set if rcg is in disabled
> state. Since the new configuration is not yet updated in h/w, dirty bit of
> configuration register will be set in such case. Clear the dirty bit and
> update the rcg to proper new configuration by setting the update bit before
> enabling the rcg.
> 

If I understand correctly you're saying that without this patch:

    devm_clk_get();
    clk_set_rate(rate);
    clk_prepare_enable();

would look like it worked (i.e. clk_get_rate() would return rate), but
in reality the clock is running at whatever the "default" rate is.

That sounds like it could use a Fixes: tag if so!

Thanks,
Andrew