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Message-Id: <1689693645-28254-4-git-send-email-quic_krichai@quicinc.com>
Date:   Tue, 18 Jul 2023 20:50:44 +0530
From:   Krishna chaitanya chundru <quic_krichai@...cinc.com>
To:     manivannan.sadhasivam@...aro.org
Cc:     helgaas@...nel.org, linux-pci@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        quic_vbadigan@...cinc.com, quic_nitegupt@...cinc.com,
        quic_skananth@...cinc.com, quic_ramkri@...cinc.com,
        krzysztof.kozlowski@...aro.org,
        Krishna chaitanya chundru <quic_krichai@...cinc.com>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        devicetree@...r.kernel.org (open list:OPEN FIRMWARE AND FLATTENED
        DEVICE TREE BINDINGS)
Subject: [PATCH v9 3/4] arm: dts: qcom: sdx55: Add CPU PCIe interconnect path

Add cpu-pcie interconnect path to sdx65 platform.

Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
---
 arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
index df3cd9c..a7c0c26 100644
--- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
@@ -422,8 +422,9 @@
 			interrupt-names = "global",
 					  "doorbell";
 
-			interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>;
-			interconnect-names = "pcie-mem";
+			interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>,
+					<&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
 
 			resets = <&gcc GCC_PCIE_BCR>;
 			reset-names = "core";
-- 
2.7.4

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