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Message-ID: <PH0PR11MB519187156E9F27AA52C87063F138A@PH0PR11MB5191.namprd11.prod.outlook.com>
Date:   Tue, 18 Jul 2023 07:43:41 +0000
From:   "Li, Meng" <Meng.Li@...driver.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        "dinguyen@...nel.org" <dinguyen@...nel.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>,
        "conor+dt@...nel.org" <conor+dt@...nel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH] usb: dwc2: add new compatible for Intel SoCFPGA Stratix10
 platform



> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Sent: Tuesday, July 18, 2023 2:11 PM
> To: Li, Meng <Meng.Li@...driver.com>; dinguyen@...nel.org;
> robh+dt@...nel.org; krzysztof.kozlowski+dt@...aro.org; conor+dt@...nel.org;
> devicetree@...r.kernel.org
> Cc: linux-kernel@...r.kernel.org
> Subject: Re: [PATCH] usb: dwc2: add new compatible for Intel SoCFPGA Stratix10
> platform
> 
> CAUTION: This email comes from a non Wind River email account!
> Do not click links or open attachments unless you recognize the sender and
> know the content is safe.
> 
> On 18/07/2023 05:08, Meng Li wrote:
> > Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on
> > the Stratix platform also does not support clock-gating. The commit
> > 3d8d3504d233("usb: dwc2: Add platform specific data for Intel's
> > Agilex") had fixed this issue. So, add the essential compatible to
> > also use the specific data on Stratix10 platform.
> >
> > Signed-off-by: Meng Li <Meng.Li@...driver.com>
> > ---
> >  arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> > b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> > index ea788a920eab..b8dd5509c214 100644
> > --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> > +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> > @@ -490,7 +490,7 @@ usbphy0: usbphy@0 {
> >               };
> >
> >               usb0: usb@...00000 {
> > -                     compatible = "snps,dwc2";
> > +                     compatible = "intel,socfpga-agilex-hsotg",
> > + "snps,dwc2";
> 
> You miss SoC specific compatible.
> 

Sorry! I don't understand what do you mean about SoC specific compatible.
I think agilex is the soc specific.
Could you please show your example?

Thanks,
LImeng

> Best regards,
> Krzysztof

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