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Message-ID: <a3bb6e88-9b0f-c504-df35-96892395f188@quicinc.com>
Date: Wed, 19 Jul 2023 12:03:11 +0530
From: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>
To: Manivannan Sadhasivam <mani@...nel.org>
CC: <manivannan.sadhasivam@...aro.org>, <helgaas@...nel.org>,
<linux-pci@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <quic_vbadigan@...cinc.com>,
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Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
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Subject: Re: [PATCH v9 3/4] arm: dts: qcom: sdx55: Add CPU PCIe interconnect
path
On 7/19/2023 10:11 AM, Manivannan Sadhasivam wrote:
> On Tue, Jul 18, 2023 at 08:50:44PM +0530, Krishna chaitanya chundru wrote:
>> Add cpu-pcie interconnect path to sdx65 platform.
> sdx55 and please mention "PCIe RC". Perhaps you should also add "missing"?
>
> - Mani
I will reactify it.
for "PCIe RC" you mean "PCIe EP" as this endpoint node
-KC
>
>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
>> ---
>> arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 5 +++--
>> 1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
>> index df3cd9c..a7c0c26 100644
>> --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
>> +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
>> @@ -422,8 +422,9 @@
>> interrupt-names = "global",
>> "doorbell";
>>
>> - interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>;
>> - interconnect-names = "pcie-mem";
>> + interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>,
>> + <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>;
>> + interconnect-names = "pcie-mem", "cpu-pcie";
>>
>> resets = <&gcc GCC_PCIE_BCR>;
>> reset-names = "core";
>> --
>> 2.7.4
>>
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