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Message-ID: <20230719074055.GB9312@thinkpad>
Date: Wed, 19 Jul 2023 13:10:55 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Krishna chaitanya chundru <quic_krichai@...cinc.com>
Cc: manivannan.sadhasivam@...aro.org, helgaas@...nel.org,
linux-pci@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org, quic_vbadigan@...cinc.com,
quic_nitegupt@...cinc.com, quic_skananth@...cinc.com,
quic_ramkri@...cinc.com, krzysztof.kozlowski@...aro.org,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>
Subject: Re: [PATCH v10 3/4] arm: dts: qcom: sdx55: Add CPU PCIe EP
interconnect path
On Wed, Jul 19, 2023 at 12:50:17PM +0530, Krishna chaitanya chundru wrote:
> Add cpu-pcie interconnect path for PCIe EP to sdx55 platform.
>
> Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
- Mani
> ---
> arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
> index df3cd9c..a7c0c26 100644
> --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
> @@ -422,8 +422,9 @@
> interrupt-names = "global",
> "doorbell";
>
> - interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>;
> - interconnect-names = "pcie-mem";
> + interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>,
> + <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>;
> + interconnect-names = "pcie-mem", "cpu-pcie";
>
> resets = <&gcc GCC_PCIE_BCR>;
> reset-names = "core";
> --
> 2.7.4
>
--
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