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Message-Id: <20230719025509.3007986-2-Meng.Li@windriver.com>
Date:   Wed, 19 Jul 2023 10:55:07 +0800
From:   Meng Li <Meng.Li@...driver.com>
To:     gregkh@...uxfoundation.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
        dinguyen@...nel.org, hminas@...opsys.com,
        linux-usb@...r.kernel.org, devicetree@...r.kernel.org
Cc:     linux-kernel@...r.kernel.org, meng.li@...driver.com
Subject: [PATCH 1/3] usb: dwc2: Add platform specific data for Intel Stratix10 platform

Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on
the Stratix platform also does not support clock-gating. So, refer to
commit 3d8d3504d233("usb: dwc2: Add platform specific data for
Intel's Agilex"), add platform specific data for Intel Stratix10 platform.

Signed-off-by: Meng Li <Meng.Li@...driver.com>
---
 drivers/usb/dwc2/params.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 8eab5f38b110..3d085ae1ecd8 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -267,6 +267,8 @@ const struct of_device_id dwc2_of_match_table[] = {
 	  .data = dwc2_set_stm32mp15_hsotg_params },
 	{ .compatible = "intel,socfpga-agilex-hsotg",
 	  .data = dwc2_set_socfpga_agilex_params },
+	{ .compatible = "intel,socfpga-stratix10-hsotg",
+	  .data = dwc2_set_socfpga_agilex_params },
 	{},
 };
 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
-- 
2.34.1

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