linux-kernel - Re: [PATCH] clk: qcom: clk-rcg2: Fix wrong RCG clock rate for high parent frequencies

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Message-ID: <d68cc9a4-d4a4-17b1-c6fd-d128b82a818e@linaro.org>
Date:   Thu, 20 Jul 2023 18:08:03 +0200
From:   Konrad Dybcio <konrad.dybcio@...aro.org>
To:     Devi Priya <quic_devipriy@...cinc.com>, andersson@...nel.org,
        agross@...nel.org, mturquette@...libre.com, sboyd@...nel.org,
        linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org
Cc:     quic_saahtoma@...cinc.com
Subject: Re: [PATCH] clk: qcom: clk-rcg2: Fix wrong RCG clock rate for high
 parent frequencies

On 20.07.2023 10:33, Devi Priya wrote:
> If the parent clock rate is greater than unsigned long max/2 then
> integer overflow happens when calculating the clock rate on 32-bit systems.
> As RCG2 uses half integer dividers, the clock rate is first being
> multiplied by 2 which will overflow the unsigned long max value. So, use
> unsigned long long for rate computations to avoid overflow.
> 
> Signed-off-by: Devi Priya <quic_devipriy@...cinc.com>
> ---
>  drivers/clk/qcom/clk-rcg2.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
> index e22baf3a7112..42d00b134975 100644
> --- a/drivers/clk/qcom/clk-rcg2.c
> +++ b/drivers/clk/qcom/clk-rcg2.c
> @@ -156,18 +156,18 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
>   *            hid_div       n
>   */
>  static unsigned long
> -calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
> +calc_rate(unsigned long parent_rate, u32 m, u32 n, u32 mode, u32 hid_div)
>  {
> +	u64 rate = parent_rate;
This should not be necessary.. You're being passed a copy of
the original value, which you can operate on.

Otherwise, LGTM

Konrad