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Message-Id: <20230720-deck-accent-0dffdaf52958@spud>
Date: Thu, 20 Jul 2023 17:29:50 +0100
From: Conor Dooley <conor@...nel.org>
To: Conor Dooley <conor@...nel.org>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Hal Feng <hal.feng@...rfivetech.com>,
linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Emil Renner Berthing <emil.renner.berthing@...onical.com>,
Xingyu Wu <xingyu.wu@...rfivetech.com>
Cc: Conor Dooley <conor.dooley@...rochip.com>,
linux-kernel@...r.kernel.org,
William Qiu <william.qiu@...rfivetech.com>,
linux-clk@...r.kernel.org
Subject: Re: (subset) [PATCH v7 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC
From: Conor Dooley <conor.dooley@...rochip.com>
On Mon, 17 Jul 2023 10:30:33 +0800, Xingyu Wu wrote:
> This patch serises are to add PLL clocks driver and providers by writing
> and reading syscon registers for the StarFive JH7110 RISC-V SoC. And add
> documentation and nodes to describe StarFive System Controller(syscon)
> Registers. This patch serises are based on Linux 6.4.
>
> PLLs are high speed, low jitter frequency synthesizers in JH7110.
> Each PLL clock works in integer mode or fraction mode by some dividers,
> and the dividers are set in several syscon registers.
> The formula for calculating frequency is:
> Fvco = Fref * (NI + NF) / M / Q1
>
> [...]
Applied to riscv-dt-for-next, thanks!
[6/7] riscv: dts: starfive: jh7110: Add syscon nodes
https://git.kernel.org/conor/c/3fcbcfc496f0
[7/7] riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node
https://git.kernel.org/conor/c/3e6670a28b00
Thanks,
Conor.
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